2.2 Place and Route

The Place and Route process requires the I/O, the timing, and the floor planner constraints. This design includes the following constraint files in the Constraint Manager window:

  • The io_constraints.pdc file for the I/O assignments
  • The top_derived_constaints.sdc file for timing constraints
  • The timing_user_constraints.sdc file for creating the JTAG clock with 30 MHz frequency
To Place and Route, perform the following step:
  • In the Design Flow window, double-click Place and Route.

    When place and route is successful, a green tick mark appears next to Place and Route.

Important: The top_place_and_route_constraint_coverage.xml file is recommended to be viewed for place and route constraint coverage.