46.8 Wake-Up Time
Conditions:
- VDDIO/VDDANA = 3.3V
- LDO Regulation mode
- CPU clock = OSC16M @ 4 MHz
- One Wait-state
- Cache enabled
- Flash Fast Wake-up enabled (NVMCTRL.CTRLB.FWUP = 1)
- Flash in WAKEUPINSTANT mode (NVMCTRL.CTRLB.SLEEPPRM = 1)
Measurement Method:
For Idle and Standby, the CPU sets an I/O by writing PORT->IOBUS without jumping in an interrupt handler (Cortex M23 register PRIMASK = 1). The wake-up time is measured between the edge of the wake-up input signal and the edge of the GPIO pin.
For Off mode, the exit of the mode is done through the reset pin, the time
is measured between the falling edge of the RESETN signal (with the minimum reset pulse
length), and the set of the I/O which is done by the first executed instructions after
Reset.
| Sleep Mode | Condition | Typ | Unit | |
|---|---|---|---|---|
| Idle | PL2 or PL0 | 1.5 | μs | |
| Standby | PL0 | PDSW domain in retention | 5.3 | |
| PDSW domain in active | 2.6 | |||
| PL2 Voltage scaling at default values: SUPC >VREG.VSVSTEP=0 SUPC > VREG.VSPER=0 |
PDSW domain in retention | 76 | ||
| PDSW domain in active | 75 | |||
| PL2 Voltage scaling at fastest setting: SUPC > VREG.VSVSTEP=15 SUPC > VREG.VSPER=0 |
PDSW domain in retention | 16 | ||
| PDSW domain in active | 15 | |||
| OFF | L10 with BOOTOPT=0 | 3.2 | ms | |
| L11 with BOOTOPT=0 | 4.1 | |||
| L10 or L11 with BOOTOPT=1, BS = 0x40 | 210 | |||
| L10 or L11 with BOOTOPT=1, BS = 0x80 | 410 | |||
| L10 or L11 with BOOTOPT=2, BS = 0x40 | 210 | |||
| L10 or L11 with BOOTOPT=2, BS = 0x80 | 410 | |||
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.