43.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized

Bit 76543210 
  RUNSTDBY    ENABLESWRST 
Access R/WR/WR/W 
Reset 000 

Bit 6 – RUNSTDBY Run in Standby

This bit is not synchronized

ValueDescription
0 The DAC output buffer is disabled in standby sleep mode.
1 The DAC output buffer can be enabled in standby sleep mode.

Bit 1 – ENABLE Enable DAC Controller

Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the corresponding bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

ValueDescription
0 The peripheral is disabled or being disabled.
1 The peripheral is enabled or being enabled.

Bit 0 – SWRST Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the DAC to their initial state, and the DAC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Note:
  1. When the CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to know when the reset operation is complete.
  2. During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
ValueDescription
0 There is no reset operation ongoing.
1 The reset operation is ongoing.