19.8.6 AHB Mask
| Name: | AHBMASK |
| Offset: | 0x10 |
| Reset: | 0x000001FFF |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRAM | Reserved | Reserved | Reserved | Reserved | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 1 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NVMCTRL | PAC | Reserved | DSU | DMAC | APBC | APBB | APBA | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 12 – TRAM TRAM AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the TRAM is stopped |
| 1 | The AHB clock for the TRAM is enabled |
Bit 11 – Reserved Must Be Set to 1
Bit 10 – Reserved Must Be Set to 1
Bit 9 – Reserved Must Be Set to 1
Bit 8 – Reserved Must Be Set to 1
Bit 7 – NVMCTRL NVMCTRL AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the NVMCTRL is stopped |
| 1 | The AHB clock for the NVMCTRL is enabled |
Bit 6 – PAC PAC AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the PAC is stopped. |
| 1 | The AHB clock for the PAC is enabled. |
Bit 5 – Reserved Must Be Set to 1
Bit 4 – DSU DSU AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the DSU is stopped. |
| 1 | The AHB clock for the DSU is enabled. |
Bit 3 – DMAC DMAC AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the DMAC is stopped. |
| 1 | The AHB clock for the DMAC is enabled. |
Bit 2 – APBC AHB-APB Bridge C AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the APBC is stopped. |
| 1 | The AHB clock for the APBC is enabled |
Bit 1 – APBB AHB-APB Bridge B AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the APBB is stopped. |
| 1 | The AHB clock for the APBB is enabled. |
Bit 0 – APBA AHB-APB Bridge A AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the APBA is stopped. |
| 1 | The AHB clock for the APBA is enabled. |