19.8.9 APBC Mask
| Name: | APBCMASK |
| Offset: | 0x1C |
| Reset: | 0x00001FFF for 32-pin packages / 0x00001FF7 for 24-pin packages |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OPAMP | CCL | TRNG | PTC | DAC | |||||
| Access | R/W | R | R | R | R | ||||
| Reset | 1 | 1 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADC | TC2 | TC1 | TC0 | SERCOM2 | SERCOM1 | SERCOM0 | EVSYS | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 12 – OPAMP OPAMP APBC Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the OPAMP is stopped. |
| 1 | The APBC clock for the OPAMP is enabled. |
Bit 11 – CCL CCL APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the CCL is stopped. |
| 1 | The APBC clock for the CCL is enabled. |
Bit 10 – TRNG TRNG APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the TRNG is stopped. |
| 1 | The APBC clock for the TRNG is enabled. |
Bit 9 – PTC PTC APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the PTC is stopped. |
| 1 | The APBC clock for the PTC is enabled. |
Bit 8 – DAC DAC APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the DAC is stopped. |
| 1 | The APBC clock for the DAC is enabled. |
Bit 7 – ADC ADC APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the ADC is stopped. |
| 1 | The APBC clock for the ADC is enabled. |
Bit 6 – TC2 TC2 APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the TC2 is stopped. |
| 1 | The APBC clock for the TC2 is enabled. |
Bit 5 – TC1 TC1 APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the TC1 is stopped. |
| 1 | The APBC clock for the TC1 is enabled. |
Bit 4 – TC0 TC0 APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the TC0 is stopped. |
| 1 | The APBC clock for the TC0 is enabled. |
Bit 3 – SERCOM2 SERCOM2 APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the SERCOM2 is stopped. |
| 1 | The APBC clock for the SERCOM2 is enabled. |
Bit 2 – SERCOM1 SERCOM1 APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the SERCOM1 is stopped. |
| 1 | The APBC clock for the SERCOM1 is enabled. |
Bit 1 – SERCOM0 SERCOM0 APBC Mask Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the SERCOM0 is stopped. |
| 1 | The APBC clock for the SERCOM0 is enabled. |
Bit 0 – EVSYS EVSYS APBC Clock Enable
| Value | Description |
|---|---|
| 0 | The APBC clock for the EVSYS is stopped. |
| 1 | The APBC clock for the EVSYS is enabled. |