20.11.5 TxCLKCON

Timer Clock Source Selection Register

Name:	TxCLKCON
Address:	0x290,0x296,0x29C


Bit	7	6	5	4	3	2	1	0
					CS[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CS[3:0] Timer Clock Source Selection bits

Table 20-3. Clock Source Selection
CS[3:0]	Clock Source
CS[3:0]	Timer2	Timer4	Timer6
`1111`	Reserved	Reserved	Reserved
`1110`	CLC4_out	CLC4_out	CLC4_out
`1101`	CLC3_out	CLC3_out	CLC3_out
`1100`	CLC2_out	CLC2_out	CLC2_out
`1011`	CLC1_out	CLC1_out	CLC1_out
`1010`	ZCD1_output	ZCD1_output	ZCD1_output
`1001`	NCO1_out	NCO1_out	NCO1_out
`1000`	CLKR	CLKR	CLKR
`0111`	SOSC	SOSC	SOSC
`0110`	MFINTOSC(31.25 kHz)	MFINTOSC(31.25 kHz)	MFINTOSC(31.25 kHz)
`0101`	MFINTOSC(500 kHz)	MFINTOSC(500 kHz)	MFINTOSC(500 kHz)
`0100`	LFINTOSC	LFINTOSC	LFINTOSC
`0011`	HFINTOSC(32 MHz)	HFINTOSC(32 MHz)	HFINTOSC(32 MHz)
`0010`	F_OSC	F_OSC	F_OSC
`0001`	F_OSC/4	F_OSC/4	F_OSC/4
`0000`	T2INPPS	T4INPPS	T6INPPS

Value	Description
n	See the Clock Source Selection table

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