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28-Pin Full-Featured, Low Pin Count Microcontrollers with XLP
Description
Core Features
Memory
Operating Characteristics
eXtreme Low-Power (XLP) Features
Power-Saving Operation Modes
Digital Peripherals
Analog Peripherals
Flexible Oscillator Structure
PIC16(L)F184XX Family Types
Packages
Pin Diagrams
1 28-Pin Diagrams
Pin Allocation Tables
1 Device Overview
1.1 New Core Features
1.2 Other Special Features
1.3 Details on Individual Family Members
1.4 Register and Bit Naming Conventions
1.5 Register Legend
2 Guidelines for Getting Started with PIC16(L)F18455/56 Microcontrollers
2.1 Basic Connection Requirements
2.2 Power Supply Pins
2.3 Master Clear (MCLR) Pin
2.4 In-Circuit Serial Programming™ (ICSP™) Pins
2.5 External Oscillator Pins
2.6 Unused I/Os
3 Enhanced Mid-Range CPU
3.1 Automatic Interrupt Context Saving
3.2 16-Level Stack with Overflow and Underflow
3.3 File Select Registers
3.4 Instruction Set
4 Device Configuration
4.1 Configuration Words
4.2 Code Protection
4.3 Write Protection
4.4 User ID
4.5 Device ID and Revision ID
4.6 Register Summary - Configuration Words
4.7 Register Definitions: Configuration Words
4.8 Register Summary - Device and Revision
4.9 Register Definitions: Device and Revision
5 Memory Organization
5.1 Program Memory Organization
5.2 Memory Access Partition (MAP)
5.3 Data Memory Organization
5.4 PCL and PCLATH
5.5 Stack
5.6 Indirect Addressing
5.7 Register Summary - Memory and Status
5.8 Register Definitions: Memory and Status
5.9 Register Summary - Shadow Registers
5.10 Register Definitions: Shadow Registers
5.11 Device Configuration Information
5.12 Device Information Area
6 NVM - Nonvolatile Memory Control
6.1 Program Flash Memory
6.2 Data EEPROM
6.3 FSR and INDF Access
6.4 NVMREG Access
6.5 Register Summary - NVM Control
6.6 Register Definitions: Nonvolatile Memory
7 Interrupts
7.1 Operation
7.2 Interrupt Latency
7.3 Interrupts During Sleep
7.4 INT Pin
7.5 Automatic Context Saving
7.6 Register Summary - Interrupt Control
7.7 Register Definitions: Interrupt Control
8 OSC - Oscillator Module
8.1 Overview
8.2 Clock Source Types
8.3 Clock Switching
8.4 Fail-Safe Clock Monitor
8.5 Register Summary - OSC
8.6 Register Definitions: Oscillator Control
9 REFCLK - Reference Clock Output Module
9.1 Clock Source
9.2 Programmable Clock Divider
9.3 Selectable Duty Cycle
9.4 Operation in Sleep Mode
9.5 Register Summary - Reference CLK
9.6 Register Definitions: Reference Clock
10 Resets
10.1 Power-on Reset (POR)
10.2 Brown-out Reset (BOR)
10.3 Low-Power Brown-out Reset (LPBOR)
10.4 MCLR Reset
10.5 Windowed Watchdog Timer (WWDT) Reset
10.6 RESET Instruction
10.7 Stack Overflow/Underflow Reset
10.8 Programming Mode Exit
10.9 Power-up Timer (PWRT)
10.10 Start-up Sequence
10.11 Memory Execution Violation
10.12 Determining the Cause of a Reset
10.13 Register Summary - BOR Control and Power Control
10.14 Register Definitions: Power Control
11 WWDT - Windowed Watchdog Timer
11.1 Independent Clock Source
11.2 WWDT Operating Modes
11.3 Time-out Period
11.4 Watchdog Window
11.5 Clearing the WWDT
11.6 Operation During Sleep
11.7 Register Summary - WDT Control
11.8 Register Definitions: Windowed Watchdog Timer Control
12 Power-Saving Operation Modes
12.1 Doze Mode
12.2 Sleep Mode
12.3 Idle Mode
12.4 Register Summary - Power Savings Control
12.5 Register Definitions: Power Savings Control
13 PMD - Peripheral Module Disable
13.1 Disabling a Module
13.2 Enabling a Module
13.3 System Clock Disable
13.4 Register Summary - PMD
13.5 Register Definitions: Peripheral Module Disable
14 I/O Ports
14.1 PORT Availability
14.2 I/O Ports Description
14.3 I/O Priorities
14.4 PORTx Registers
14.5 Register Summary - Input/Output
14.6 Register Definitions: Port Control
15 IOC - Interrupt-On-Change
15.1 Enabling the Module
15.2 Individual Pin Configuration
15.3 Interrupt Flags
15.4 Operation in Sleep
15.5 Register Summary - Interrupt-on-Change
15.6 Register Definitions: Interrupt-on-Change Control
16 PPS - Peripheral Pin Select Module
16.1 PPS Inputs
16.2 PPS Outputs
16.3 Bidirectional Pins
16.4 PPS Lock
16.5 PPS1WAY Bit
16.6 Operation During Sleep
16.7 Effects of a Reset
16.8 Register Summary - PPS
16.9 Register Definitions: PPS Input and Output Selection
17 CLC - Configurable Logic Cell
17.1 CLC Setup
17.2 CLC Interrupts
17.3 Output Mirror Copies
17.4 Effects of a Reset
17.5 Operation During Sleep
17.6 CLC Setup Steps
17.7 Register Summary - CLC Control
17.8 Register Definitions: Configurable Logic Cell
18 TMR0 - Timer0 Module
18.1 Timer0 Operation
18.2 Clock Selection
18.3 Timer0 Output and Interrupt
18.4 Operation During Sleep
18.5 Register Summary - Timer0
18.6 Register Definitions: Timer0 Control
19 TMR1 - Timer1 Module with Gate Control
19.1 Timer1 Operation
19.2 Clock Source Selection
19.3 Timer1 Prescaler
19.4 Secondary Oscillator
19.5 Timer1 Operation in Asynchronous Counter Mode
19.6 Timer1 16-Bit Read/Write Mode
19.7 Timer1 Gate
19.8 Timer1 Interrupt
19.9 Timer1 Operation During Sleep
19.10 CCP Capture/Compare Time Base
19.11 CCP Special Event Trigger
19.12 Peripheral Module Disable
19.13 Register Summary - Timer1
19.14 Register Definitions: Timer1
20 TMR2 - Timer2 Module
20.1 Timer2 Operation
20.2 Timer2 Output
20.3 External Reset Sources
20.4 Timer2 Interrupt
20.5 PSYNC Bit
20.6 CSYNC Bit
20.7 Operating Modes
20.8 Operation Examples
20.9 Timer2 Operation During Sleep
20.10 Register Summary - Timer2
20.11 Register Definitions: Timer2 Control
21 SMT - Signal Measurement Timer
21.1 SMT Operation
21.2 Register Summary - SMT Control
21.3 Register Definitions: SMT Control
22 Capture/Compare/PWM Module
22.1 CCP Module Configuration
22.2 Capture Mode
22.3 Compare Mode
22.4 PWM Overview
22.5 Register Summary - CCP Control
22.6 Register Definitions: CCP Control
23 CCP/PWM Timer Resource Selection
23.1 Register Summary - Timer Selection Registers for CCP/PWM
23.2 Register Definitions: CCP/PWM Timer Selection
24 PWM - Pulse-Width Modulation
24.1 Fundamental Operation
24.2 PWM Output Polarity
24.3 PWM Period
24.4 PWM Duty Cycle
24.5 PWM Resolution
24.6 Operation in Sleep Mode
24.7 Changes in System Clock Frequency
24.8 Effects of Reset
24.9 Setup for PWM Operation Using PWMx Output Pins
24.10 Setup for PWM Operation to Other Device Peripherals
24.11 Register Summary - Registers Associated with PWM
24.12 Register Definitions: PWM Control
25 CWG - Complementary Waveform Generator
25.1 Fundamental Operation
25.2 Operating Modes
25.3 Start-up Considerations
25.4 Clock Source
25.5 Selectable Input Sources
25.6 Output Control
25.7 Dead-Band Control
25.8 Rising Edge and Reverse Dead Band
25.9 Falling Edge and Forward Dead Band
25.10 Dead-Band Jitter
25.11 Auto-Shutdown
25.12 Operation During Sleep
25.13 Configuring the CWG
25.14 Register Summary - CWG Control
25.15 Register Definitions: CWG Control
26 NCO - Numerically Controlled Oscillator
26.1 NCO Operation
26.2 Fixed Duty Cycle Mode
26.3 Pulse Frequency Mode
26.4 Output Polarity Control
26.5 Interrupts
26.6 Effects of a Reset
26.7 Operation in Sleep
26.8 Register Summary - NCO
26.9 Register Definitions: NCO
27 DSM - Data Signal Modulator Module
27.1 DSM Operation
27.2 Modulator Signal Sources
27.3 Carrier Signal Sources
27.4 Carrier Synchronization
27.5 Carrier Source Polarity Select
27.6 Programmable Modulator Data
27.7 Modulated Output Polarity
27.8 Operation in Sleep Mode
27.9 Effects of a Reset
27.10 Peripheral Module Disable
27.11 Register Summary - DSM
27.12 Register Definitions: Modulation Control
28 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
28.1 EUSART Asynchronous Mode
28.2 EUSART Baud Rate Generator (BRG)
28.3 EUSART Synchronous Mode
28.4 EUSART Operation During Sleep
28.5 Register Summary - EUSART
28.6 Register Definitions: EUSART Control
29 MSSP - Host Synchronous Serial Port Module
29.1 SPI Mode Overview
29.2 SPI Mode Operation
29.3 I2C Mode Overview
29.4 I2C Mode Operation
29.5 I2C Client Mode Operation
29.6 I2C Host Mode
29.7 Baud Rate Generator
29.8 Register Summary - MSSP Control
29.9 Register Definitions: MSSP Control
30 FVR - Fixed Voltage Reference
30.1 Independent Gain Amplifiers
30.2 FVR Stabilization Period
30.3 Register Summary - FVR
30.4 Register Definitions: FVR Control
31 Temperature Indicator Module
31.1 Module Operation
31.2 Minimum Operating VDD
31.3 Temperature Indicator Range
31.4 Estimation of Temperature
31.5 ADC Acquisition Time
32 ADC2 - Analog-to-Digital Converter
32.1 ADC Configuration
32.2 ADC Operation
32.3 ADC Acquisition Requirements
32.4 ADC Charge Pump
32.5 Capacitive Voltage Divider (CVD) Features
32.6 Computation Operation
32.7 Register Summary - ADC Control
32.8 Register Definitions: ADC Control
33 DAC - 5-Bit Digital-to-Analog Converter
33.1 Output Voltage Selection
33.2 Ratiometric Output Level
33.3 DAC Voltage Reference Output
33.4 Operation During Sleep
33.5 Effects of a Reset
33.6 Register Summary - DAC Control
33.7 Register Definitions: DAC Control
34 CMP - Comparator Module
34.1 Comparator Overview
34.2 Comparator Control
34.3 Comparator Hysteresis
34.4 Operation with Timer1 Gate
34.5 Comparator Interrupt
34.6 Comparator Positive Input Selection
34.7 Comparator Negative Input Selection
34.8 Comparator Response Time
34.9 Analog Input Connection Considerations
34.10 CWG1 Auto-Shutdown Source
34.11 ADC Auto-Trigger Source
34.12 Even Numbered Timers Reset
34.13 Operation in Sleep Mode
34.14 Register Summary - Comparator
34.15 Register Definitions: Comparator Control
35 ZCD - Zero-Cross Detection Module
35.1 External Resistor Selection
35.2 ZCD Logic Output
35.3 ZCD Logic Polarity
35.4 ZCD Interrupts
35.5 Correction for ZCPINV Offset
35.6 Handling VPEAK Variations
35.7 Operation During Sleep
35.8 Effects of a Reset
35.9 Disabling the ZCD Module
35.10 Register Summary - ZCD Control
35.11 Register Definitions: ZCD Control
36 Register Summary
37 Instruction Set Summary
37.1 Read-Modify-Write Operations
37.2 Standard Instruction Set
38 ICSP™ - In-Circuit Serial Programming™
38.1 High-Voltage Programming Entry Mode
38.2 Low-Voltage Programming Entry Mode
38.3 Common Programming Interfaces
39 Electrical Specifications
39.1 Absolute Maximum Ratings(†)
39.2 Standard Operating Conditions
39.3 DC Characteristics
39.4 AC Characteristics
40 DC and AC Characteristics Graphs and Tables
40.1 Graphs
41 Packaging Information
41.1 Package Marking
41.2 Package Drawings
42 Revision History
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