1.3 Details on Individual Family Members

The devices of the PIC16(L)F184XX family described in the current data sheet are available in 28-pin packages. The block diagram for this device is shown in Figure 1-1.

The devices have the following differences:

Program Flash Memory.
Data Memory SRAM.
Data Memory EEPROM.
A/D channels.
I/O ports.
Enhanced USART.
Input Voltage Range/Power Consumption.

All other features for devices in this family are identical. These are summarized in the following “Device Features” table.

The pinouts for all devices are listed in the pin summary tables.

Table 1-1. Device Features
Features	PIC16(L)F18455	PIC16(L)F18456
Program Memory (KBytes)	14	28
Program Memory (Instructions)	8192	16384
Data Memory (Bytes)	1024	2048
Data EEPROM Memory (Bytes)	256	256
Packages	28 - SPDIP 28 - SSOP 28 - SOIC (7.5 mm) 28 - VQFN (4x4)	28 - SPDIP 28 - SSOP 28 - SOIC (7.5 mm) 28 - VQFN (4x4)
I/O Ports	A, B, C	A, B, C
Capture/Compare/PWM Modules (CCP)	5	5
Configurable Logic Cell (CLC)	4	4
10-Bit Pulse-Width Modulator (PWM)	2	2
12-Bit Analog-to-Digital Module (ADC²) with Computation Accelerator	24 channels	24 channels
5-Bit Digital-to-Analog Module (DAC)	1	1
Comparators	2	2
Numerical Contolled Oscillator (NCO)	1	1
Interrupt Sources	47	47
Timers (16-/8-bit)	4	4
Serial Communications	2 MSSP 2 EUSART	2 MSSP 2 EUSART
Complementary Waveform Generator (CWG)	3	3
Zero-Cross Detect (ZCD)	1	1
Data Signal Modulator (DSM)	1	1
Reference Clock Output Module	1	1
Peripheral Pin Select (PPS)	YES	YES
Peripheral Module Disable (PMD)	YES	YES
Programmable Brown-out Reset (BOR)	YES	YES
Resets (and Delays)	POR, BOR, `RESET` Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT	POR, BOR, `RESET` Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT
Instruction Set	50 instructions 16-levels hardware stack	50 instructions 16-levels hardware stack
Operating Frequency	DC – 32 MHz	DC – 32 MHz

Figure 1-1. PIC16(L)F18455/56 Device Block Diagram