16.1 PPS Inputs

Each peripheral has a PPS register with which the input pin to the peripheral is selected. Although each peripheral has its own PPS input selection register, the selections are identical for every peripheral, as shown in xxxPPS. Not all ports are available for input, as shown in Table 16-1.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = INT for the INTPPS register.
Table 16-1. PPS Input Signal Routing Options
Input Signal NameInput Register NameDefault Location at POR (28-pin devices)Reset Value (xxxPPS[4:0])PORT From Which Input Is Available
INTINTPPSRB00 1000AB—
T0CKIT0CKIPPSRA40 0100AB—
T1CKIT1CKIPPSRC01 0000A—C
T1GT1GPPSRB50 1101—BC
T2INT2INPPSRC31 0011A—C
T3CKIT3CKIPPSRC01 0000—BC
T3GT3GPPSRC01 0000A—C
T4INT4INPPSRC51 0101—BC
T5CKIT5CKIPPSRC21 0010A—C
T5GT5GPPSRB40 1100—BC
T6INT6INPPSRB70 1111—BC
MDCARLMDCARLPPSRA30 0001A—C
MDCARHMDCARHPPSRA40 0100A—C
MDSRCMDSRCPPSRA50 0101A—C
CCP1INCCP1INPPSRC21 0010—BC
CCP2INCCP2INPPSRC11 0001—BC
CCP3INCCP3INPPSRB50 1101—BC
CCP4INCCP4INPPSRB00 1000—BC
CCP5INCCP5INPPSRA40 0100A—C
CWG1INCWG1INPPSRB00 1000—BC
CWG2INCWG2INPPSRB10 1001—BC
CWG3INCWG3INPPSRB20 1000—BC
CLCIN0CLCIN0PPSRA00 0000A—C
CLCIN1CLCIN1PPSRA10 0001A—C
CLCIN2CLCIN2PPSRB60 1110—BC
CLCIN3CLCIN3PPSRB70 1111—BC
ADACTADACTPPSRB40 1100—BC
SCL1/SCK1SSP1CLKPPSRC31 0011—BC
SDA1/SDI1SSP1DATPPSRC41 0100—BC
SS1SSP1SSPPSRA50 0101A—C
SCL2/SCK2SSP2CLKPPSRB10 1001—BC
SDA2/SDI2SSP2DATPPSRB20 1000—BC
SS2SSP2SSPPSRB20 1000—BC
RX1/DT1RX1PPSRC71 0111—BC
TX1/CK1CK1PPSRC61 0110—BC
RX2/DT2RX2PPSRB70 1111—BC
TX2/CK2CK2PPSRB60 1110—BC
SMT1SIGSMT1SIGPPSRC11 0001—BC
SMT1WINSMT1WINPPSRC01 0000—BC
SMT2SIGSMT2SIGPPSRB50 1101—BC
SMT2WINSMT2WINPPSRB40 1100—BC
Note:
  1. Some pads are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register.
Table 16-2. PPS Input Register Values
Desired Input PinValue to Write to Register
RE310 0011
RC701 0111
RC601 0110
RC501 0101
RC401 0100
RC301 0011
RC201 0010
RC101 0001
RC001 0000
RB700 1111
RB600 1110
RB500 1101
RB400 1100
RB300 1011
RB200 1010
RB100 1001
RB000 1000
RA700 0111
RA600 0110
RA500 0101
RA400 0100
RA300 0011
RA200 0010
RA100 0001
RA000 0000