38.13.12 CxTREC

CAN Transmit/Receive Error Count Register

Note:

The individual bytes in this multibyte register can be accessed with the following register names:
- CxTRECT: Accesses the top byte TREC[31:24]
- CxTRECU: Accesses the upper byte TREC[23:16]
- CxTRECH: Accesses the high byte TREC[15:8]
- CxTRECL: Accesses the low byte TREC[7:0]

Name:	CxTREC
Offset:	0x0134


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			TXBO	TXBP	RXBP	TXWARN	RXWARN	EWARN
Access			R	R	R	R	R	R
Reset			1	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TERRCNT[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RERRCNT[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 21 – TXBO Transmitter in Error Bus Off State

In Configuration mode, TXBO is set since the module is not on the bus.

Bit 20 – TXBP Transmitter in Error Bus Passive State

Bit 19 – RXBP Receiver in Error Bus Passive State

Bit 18 – TXWARN Transmitter in Error Warning State

Bit 17 – RXWARN Receiver in Error Warning State

Bit 16 – EWARN Transmitter or Receiver is in Error Warning State

Bits 15:8 – TERRCNT[7:0] Transmit Error Counter

Bits 7:0 – RERRCNT[7:0] Receive Error Counter

The individual bytes in this multibyte register can be accessed with the following register names: CxTRECT: Accesses the top byte TREC[31:24] CxTRECU: Accesses the upper byte TREC[23:16] CxTRECH: Accesses the high byte TREC[15:8] CxTRECL: Accesses the low byte TREC[7:0]