38.13.14 CxBDIAG1
CAN Bus Diagnostics
Register 1Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxBDIAG1T: Accesses
the top byte BDIAG1[31:24]
- CxBDIAG1U: Accesses
the upper byte BDIAG1[23:16]
- CxBDIAG1H: Accesses
the high byte BDIAG1[15:8]
- CxBDIAG1L: Accesses
the low byte BDIAG1[7:0]
| Name: | CxBDIAG1 |
| Offset: | 0x013C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | DLCMM | | | | | | | | |
| Access | R/W | | | | | | | | |
| Reset | 0 | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | TXBOERR | | NCRCERR | NSTUFERR | NFORMERR | NACKERR | NBIT1ERR | NBIT0ERR | |
| Access | R/W | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | EFMSGCNT[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | EFMSGCNT[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – DLCMM DLC
Mismatch
During a
transmission or reception, the specified DLC is larger than the PLSIZEx of the FIFO
element.
Bit 23 – TXBOERR Device Went to Bus Off
Bit 21 – NCRCERR Received Message with CRC Incorrect Checksum in Non-Data
Segment
The CRC Checksum of a received
message is considered incorrect if the CRC of the incoming message does not match
with the CRC calculated from the received data.
Bit 20 – NSTUFERR Received Message with Illegal Sequence in Non-Data
Segment
An Illegal Sequence occurs
when more than five equal bits in sequence in a part of the received message where
this is not allowed
Bit 19 – NFORMERR Received Frame with a Fixed Format Error in Non-Data
Segment
A fixed format error occurs
when a part of the incoming frame with a fixed format has the wrong
format
Bit 18 – NACKERR Transmitted Message Not Acknowledged
Transmitted message was not
Acknowledged
Bit 17 – NBIT1ERR Transmitted Message Dominant Level in Non-Data
Segment
During the non-data segment of
a message transmission, the device wanted to send a recessive level (bit of logical
value ‘1’), but the monitored bus value was
dominant
Bit 16 – NBIT0ERR Transmitted Message Dominant Level in Non-Data
Segment
During the transmission of a
message (or an Acknowledge bit, active error flag, or overload flag), the device
wanted to send a dominant level (logical value ‘0’), but the
monitored bus value was recessive. During bus off recovery, this status is set each
time a sequence of 11 recessive bits have been monitored. This enables the CPU to
monitor the proceeding of the bus off recovery sequence (indicating the bus is not
stuck at dominant or continuously disturbed).
Bits 15:0 – EFMSGCNT[15:0] Error-Free Message Counter
The individual bytes in this
multibyte register can be accessed with the following register names:
CxBDIAG1T: Accesses
the top byte BDIAG1[31:24]
CxBDIAG1U: Accesses
the upper byte BDIAG1[23:16]
CxBDIAG1H: Accesses
the high byte BDIAG1[15:8]
CxBDIAG1L: Accesses
the low byte BDIAG1[7:0]
