Introduction
1 Definitions, Acronyms and Abbreviations
2 Overall Description
3 Metrology Interface Definition
- 3.1 Metrology Control Registers
  - 3.1.1 Metrology State Control
    Metrology State Control
  - 3.1.2 Metrology Feature Control Register
    Metrology Feature Control Register
  - 3.1.3 Harmonic Control Register
    Harmonic Control Register
  - 3.1.4 Meter Type Settings Register
    Meter Type Settings Register
  - 3.1.5 Number of Line Cycles for Integration Period
    Number of Line Cycles for Integration Period
  - 3.1.6 Max Number of Samples in an Integration Period
    Max Number of Samples in an Integration Period
  - 3.1.7 Pulse Control Register x (x = 0, 1, 2)
    Pulse Control Register x (x = 0, 1, 2)
  - 3.1.8 Meter Active Power Pulse Constant
    Meter Active Power Pulse Constant
  - 3.1.9 Meter Reactive Power Pulse Constant
    Meter Reactive Power Pulse Constant
  - 3.1.10 Meter Current Pulse Constant
    Meter Current Pulse Constant
  - 3.1.11 Creep Threshold for Active Energy
    Creep Threshold for Active Energy
  - 3.1.12 Creep Threshold for Quadergy
    Creep Threshold for Quadergy
  - 3.1.13 Creep Threshold of Phase Current
    Creep Threshold of Phase Current
  - 3.1.14 Power Offset Control Register
    Power Offset Control Register
  - 3.1.15 Active Power Offset Register
    Active Power Offset Register
  - 3.1.16 Reactive Power Offset Register
    Reactive Power Offset Register
  - 3.1.17 Voltage Swell Threshold
    Voltage Swell Threshold
  - 3.1.18 Voltage Sag Threshold
    Voltage Sag Threshold
  - 3.1.19 Current Conversion Factor
    Current Conversion Factor
  - 3.1.20 Voltage Conversion Factor
    Voltage Conversion Factor
  - 3.1.21 Current Channel Magnitude Calibration Constants
    Current Channel Magnitude Calibration Constants
  - 3.1.22 Voltage Channel Magnitude Calibration Constants
    Voltage Channel Magnitude Calibration Constants
  - 3.1.23 Per-Channel Phase Calibration Constants
    Per-Channel Phase Calibration Constants
  - 3.1.24 Waveform Capture Control Register
    Waveform Capture Control Register
  - 3.1.25 Capture Buffer Size
    Capture Buffer Size
  - 3.1.26 Waveform Capture Destination Buffer Address
    Waveform Capture Destination Buffer Address
  - 3.1.27 ATSENSE ADC Control Register 0
    ATSENSE ADC Control Register 0
  - 3.1.28 ATSENSE ADC Control Register 1
    ATSENSE ADC Control Register 1
  - 3.1.29 ATSENSE ADC Control Register 2
    ATSENSE ADC Control Register 2
  - 3.1.30 Per-Phase Active Power Offset Register
    Per-Phase Active Power Offset Register
  - 3.1.31 Per-Phase Reactive Power Offset Register
    Per-Phase Reactive Power Offset Register
- 3.2 Metrology Status Registers
- 3.3 Accumulated Output Quantities
- 3.4 Harmonic Analysis Output Quantities
- 3.5 Derived Output Quantities
4 Interface between Metrology and Application
5 Annex. Meter Forms
The service type determines what meter form is being implemented and how the Metrology DSP core interprets and processes the ADC values.
6 References
7 Revision History
Microchip Information

3.1.21 Current Channel Magnitude Calibration Constants

Multiplicative magnitude calibration constants are provided for each current channel to equalize gain across all channels after an appropriate calibration procedure was exercised. All active input channels, both voltage and current, require final calibration to ensure full accuracy.

CAL_M_Ix: where x=[A, B, C or N] is used to calibrate the current channels.

Ix_RMS is the ideal RMS value of input calibration current. ACC_I_x is the 64-bit accumulated I^2-scaled quantities provided by metrology firmware. The value of N is the number of samples in the integration period provided in Metrology Status Registers.

Refer to “PIC32CXMTx Metrology User Guide” for a more detailed description.

Name:	CAL_M_Ix
Offset:	Metrology_Reg_In[31,33,35,37]
Property:	Read-Write


Bit	31	30	29	28	27	26	25	24
	CAL_M_Ix[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	23	22	21	20	19	18	17	16
	CAL_M_Ix[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	15	14	13	12	11	10	9	8
	CAL_M_Ix[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	7	6	5	4	3	2	1	0
	CAL_M_Ix[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset

Bits 31:0 – CAL_M_Ix[31:0] (sQ2.29)

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