Introduction
1 Definitions, Acronyms and Abbreviations
2 Overall Description
3 Metrology Interface Definition
- 3.1 Metrology Control Registers
  - 3.1.1 Metrology State Control
    Metrology State Control
  - 3.1.2 Metrology Feature Control Register
    Metrology Feature Control Register
  - 3.1.3 Harmonic Control Register
    Harmonic Control Register
  - 3.1.4 Meter Type Settings Register
    Meter Type Settings Register
  - 3.1.5 Number of Line Cycles for Integration Period
    Number of Line Cycles for Integration Period
  - 3.1.6 Max Number of Samples in an Integration Period
    Max Number of Samples in an Integration Period
  - 3.1.7 Pulse Control Register x (x = 0, 1, 2)
    Pulse Control Register x (x = 0, 1, 2)
  - 3.1.8 Meter Active Power Pulse Constant
    Meter Active Power Pulse Constant
  - 3.1.9 Meter Reactive Power Pulse Constant
    Meter Reactive Power Pulse Constant
  - 3.1.10 Meter Current Pulse Constant
    Meter Current Pulse Constant
  - 3.1.11 Creep Threshold for Active Energy
    Creep Threshold for Active Energy
  - 3.1.12 Creep Threshold for Quadergy
    Creep Threshold for Quadergy
  - 3.1.13 Creep Threshold of Phase Current
    Creep Threshold of Phase Current
  - 3.1.14 Power Offset Control Register
    Power Offset Control Register
  - 3.1.15 Active Power Offset Register
    Active Power Offset Register
  - 3.1.16 Reactive Power Offset Register
    Reactive Power Offset Register
  - 3.1.17 Voltage Swell Threshold
    Voltage Swell Threshold
  - 3.1.18 Voltage Sag Threshold
    Voltage Sag Threshold
  - 3.1.19 Current Conversion Factor
    Current Conversion Factor
  - 3.1.20 Voltage Conversion Factor
    Voltage Conversion Factor
  - 3.1.21 Current Channel Magnitude Calibration Constants
    Current Channel Magnitude Calibration Constants
  - 3.1.22 Voltage Channel Magnitude Calibration Constants
    Voltage Channel Magnitude Calibration Constants
  - 3.1.23 Per-Channel Phase Calibration Constants
    Per-Channel Phase Calibration Constants
  - 3.1.24 Waveform Capture Control Register
    Waveform Capture Control Register
  - 3.1.25 Capture Buffer Size
    Capture Buffer Size
  - 3.1.26 Waveform Capture Destination Buffer Address
    Waveform Capture Destination Buffer Address
  - 3.1.27 ATSENSE ADC Control Register 0
    ATSENSE ADC Control Register 0
  - 3.1.28 ATSENSE ADC Control Register 1
    ATSENSE ADC Control Register 1
  - 3.1.29 ATSENSE ADC Control Register 2
    ATSENSE ADC Control Register 2
  - 3.1.30 Per-Phase Active Power Offset Register
    Per-Phase Active Power Offset Register
  - 3.1.31 Per-Phase Reactive Power Offset Register
    Per-Phase Reactive Power Offset Register
- 3.2 Metrology Status Registers
- 3.3 Accumulated Output Quantities
- 3.4 Harmonic Analysis Output Quantities
- 3.5 Derived Output Quantities
4 Interface between Metrology and Application
5 Annex. Meter Forms
The service type determines what meter form is being implemented and how the Metrology DSP core interprets and processes the ADC values.
6 References
7 Revision History
Microchip Information

3.1.18 Voltage Sag Threshold

For each half cycle of the fundamental period, VxRMS is calculated, per phase, and compared to the value set in SAG_THRESHOLD_Vx: where x = [A, B, C], to determine if a voltage sag condition exists. For each half cycle that a voltage sag exists, the associated flag, SWAG_DET_Vx is set to 1.

A threshold is allowed for each phase and is computed using the native phase voltages, before transformation to implied 4WY service. This allows setting different thresholds for non-balanced service types.

SAG_THRESHOLD_Vx is stored in uQ0.32 format. So, set the threshold value as follows:

Name:	SAG_THRESHOLD_Vx
Offset:	Metrology_Reg_In[21-23]
Property:	Read-Write


Bit	31	30	29	28	27	26	25	24
	SAG_THRESHOLD_Vx[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	23	22	21	20	19	18	17	16
	SAG_THRESHOLD_Vx[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	15	14	13	12	11	10	9	8
	SAG_THRESHOLD_Vx[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	7	6	5	4	3	2	1	0
	SAG_THRESHOLD_Vx[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset

Bits 31:0 – SAG_THRESHOLD_Vx[31:0] (uQ0.32)

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