11.4 HDL Keywords and Naming Conventions

There are naming conventions you must follow when writing Verilog or VHDL code. Additionally, Verilog and VHDL have reserved words that cannot be used for signal or entity names. This section lists the naming conventions and reserved keywords for each.

VHDL:

The following naming conventions apply to VHDL designs:

VHDL is not case sensitive.
Two dashes “--” are used to begin comment lines.
Names can use alphanumeric characters and the underscore “_” character.
Names must begin with an alphabetic letter.
You may not use two underscores in a row, or use an underscore as the last character in the name.
Spaces are not allowed within names.

Object names must be unique. For example, you cannot have a signal named A and a bus named A(7 downto 0). The following is a list of the VHDL reserved keywords:


abs	downto	library	postponed	subtype
access	else	linkage	procedure	then
after	elsif	literal	process	to
alias	end	loop	pure	transport
all	entity	map	range	type
and	exit	mod	record	unaffected
architecture	file	nand	register	units
array	for	new	reject	until
assert	function	next	rem	use
attribute	generate	nor	report	variable
begin	generic	not	return	wait
block	group	null	rol	when
body	guarded	of	ror	while
buffer	if	on	select	with
bus	impure	open	severity	xnor
case	in	or	shared	xor
component	inertial	others	signal
configuration	inout	out	sla
constant	is	package	sra
disconnect	label	port	srl

Verilog:

The following naming conventions apply to Verilog HDL designs:

Verilog is case sensitive.
- Two slashes “//” are used to begin single line comments. A slash and asterisk “/*” are used to begin a multiple line comment and an asterisk and slash “*/” are used to end a multiple line comment.
Names can use alphanumeric characters, the underscore “_” character, and the dollar “$” character.
Names must begin with an alphabetic letter or the underscore.
Spaces are not allowed within names.

The following is a list of the Verilog reserved keywords:


always	endmodule	medium	reg	tranif0
and	endprimitive	module	release	tranif1
assign	endspecify	nand	repeat	tri
attribute	endtable	negedge	rnmos	tri0
begin	endtask	nmos	rpmos	tri1
buf	event	nor	rtran	triand
bufif0	for	not	rtranif0	trior
bufif1	force	notif0	rtranif1	trireg
case	forever	notif1	scalared	unsigned
casex	fork	or	signed	vectored
casez	function	output	small	wait
cmos	highz0	parameter	specify	wand
deassign	highz1	pmos	specparam	weak0
default	if	posedge	strength	weak1
defparam	ifnone	primitive	strong0	while
disable	initial	pull0	strong1	wire
edge	inout	pull1	supply0	wor
else	input	pulldown	supply1	xnor
end	integer	pullup	table	xor
endattribute	join	remos	task
endcase	large	real	time
endfunction	macromodule	realtime	tran

Related Manuals:

The following manuals provide additional information about designing and programming Microchip FPGAs using HDL design methodology:

Digital Design and Synthesis with Verilog HDL. Madhavan, Rajeev, and others. San Jose, CA: Automata Publishing Company, 1993. This book contains information to allow designers to write synthesizable designs with Verilog HDL.

HDL Chip Design. Smith, Douglas J. Madison, AL: Doone Publications, 1996. This book describes and gives examples of how to design FPGAs using VHDL and Verilog.

IEEE Standard VHDL Language Reference Manual. New York: Institute of Electrical and Electronics Engineers, Inc., 1994. This manual specifies IEEE Standard 1076-1993, which defines the VHDL standard and the use of VHDL in the creation of electronic systems.