24.3.1 Generating an EDIF Netlist

After capturing your schematic or synthesizing your design, generate an EDIF netlist from your schematic-capture or synthesis tool. Use the EDIF netlist for place-and-route in Designer. Refer to the documentation included with your schematic-capture or synthesis tool for information about generating an EDIF netlist.

Make sure to specify Verilog for the naming style when importing the EDIF netlist into Designer.