24.3.2 Generating a Structural Verilog Netlist

You can generate structural Verilog netlist using Designer or the “edn2vlog” program. Use the structural Verilog netlist for structural and timing simulation.

To generate a structural Verilog netlist using Designer,

1. Invoke Designer.
2. Import the EDIF netlist. Choose the Import Netlist File command from the File menu. The Import Netlist dialog box is displayed. Specify EDIF as the Netlist Type, GENERIC as the Edif flavor, and Verilog as the Naming Style. Type the full path name of your EDIF netlist or use the Browse button to select your design. Click OK.
3. Export a structural Verilog netlist. Choose the Export command from the File menu and then choose Netlist. The Export Netlist File dialog box is displayed. In the pull-down menu, click Verilog Files (*.v) and enter the name of the Verilog file you want to save.

To generate a structural netlist using edn2vlog,

1. Change to the directory that contains the EDIF netlist.
2. Type the following command at the UNIX or DOS prompt:

   edn2vlog FAM:{<act_fam>}
   [ EDNIN:<EdifFile1>{+<EdifFile2...>} ]
   [ VLGOUT:<Verilog_File> ]
   [ SIMTEMP:<Stimulus_template_file> ]
   <design_name>

The “EDNIN” option specifies the EDIF input file(s). You can specify multiple files with the “+” delimiter between file names. The default EDIF input file is <design_name>.edn. The “VLOGOUT” option specifies the Verilog output file names. The default Verilog output file is <design_name>.v. The “SIMTEMP” option instructs the program to generate a Verilog stimulus template file. If you do not specify this option, the program does not generate a stimulus file.