24.4 Interpreted Simulation

This chapter describes the procedures for performing functional (behavioral and structural) and timing simulation on an Microchip design by using tools that either interpret library and design files or compile them on-the-fly. Cadence NC-Verilog, Simucad SilosIII, and Synopsys VCS are simulators in this category.

This chapter includes information about creating a testbench and information about creating a command file to run a simulation in batch mode. Also, this chapter includes a description of some common Verilog simulation switches. Refer to the documentation included with your simulation tool for additional information about testbenches, command files, switches, and simulation.