23.3.2 Generating a Structural VHDL Netlist

Structural VHDL netlist files are generated automatically as part of your Libero SoC project.

You can find your VHDL netlist files in the /synthesis directory of your Libero project. For example, if your project directory is named project1, then your netlist files are in /project1/synthesis.

Some families enable you to export these files manually for use in external tools. If your device supports this feature you can export netlist files from Tools > Export > Netlist.