13.12.2 SmartDesign Design Flow

SmartDesign enables you to stitch together design blocks of different types (HDL, IP, etc ) and generate a top-level design. The Files tab lists your SmartDesign files in alphabetical order.

You can build your design using SmartDesign with the following steps:

  1. Step One – Instantiating components: In this step you will add one or more building blocks, HDL modules, components, and schematic modules from the project manager to your design. The components can be Designer blocks, cores generated from the core Catalog, and IP cores.
  2. Step Two – Connecting bus interfaces: In this step, you can add connectivity via standard bus interfaces to your design. This step is optional and can be skipped if you prefer manual connections. Components generated from the Catalog in Project Manager may include pre-defined interfaces that allow for automatic connectivity and design rule checking when used in a design.
  3. Step Three – Connecting instances: The Canvas allows you to create manual connections between ports of the instances in your design. Unused ports can be tied off to GND or VCC (disabled); input buses can be tied to a constant, and you can leave an output open by marking it as unused.
  4. Step Four – Validating the SmartDesign component: Verify the connectivity of your design using the Design Rules Check. This feature opens a special grid where design errors and warnings are organized by type and message. You can fix the errors and warnings directly in the grid. You must run the Design Rules Check again after you make your connections to check for new errors and warnings.
  5. Step Five – Generating the SmartDesign component: In this step, you generate a top-level (Top) component and its corresponding HDL file. This component can be used by downstream processes, such as synthesis and simulation, or you can add your SmartDesign HDL into another SmartDesign.

You can save your SmartDesign at any time.