13.24 Welcome to Designer

The Designer interface offers both automated and manual flows, with the push-button flow achieving the optimal solution in the shortest cycle.

Microchip's Designer software is integrated with the Libero IDE Project Manager. Use the Designer software to implement your design.

To implement your design:

  1. Right-click the top level module in the Hierarchy and choose Run Designer, or click Designer in the Project Flow window. Designer starts and loads your files from Libero.
  2. Set up your device. From the Tools menu, select Device Selection. In the Device Selection Wizard, select the die, package, speed grade, voltage, and operating conditions. Make your selections and click Next to complete the steps
  3. In Designer, click Compile in the design flow window. The log window displays the utilization of the selected device. When compile has completed, the Compile box in the Design Flow window turns green.
  4. Once you have successfully compiled your design, you can use Designer’s User's tool to optimize your design. To start a tool, simply click it in the flow tree. The include:
    Table 13-15. Tools
    ToolFunctionSupported Families

    PinEditor

    Package-level floorplanner and I/O attribute editor

    All

    ChipPlanner

    Logic viewer, placement- and floorplanning tool

    IGLOO, ProASIC3, SmartFusion, Fusion, ProASICPLUS, ProASIC, Axcelerator, RTAX-S, eX, and SX-A

    ChipEditor

    Logic viewer and placement tool

    SX, MX, 3200DX, ACT3, ACT2, ACT1

    NetlistViewer

    Design schematic viewer

    All

    SmartPower

    Power analysis tool

    IGLOO, ProASIC3, SmartFusion, Fusion, ProASICPLUS, ProASIC, Axcelerator, RTAX-S, eX, and SX-A

    SmartTime and Timer

    Static timing analysis and constraints editor (SmartTime only)

    All

    I/O Attribute Editor

    Edit I/O attributes, layout

    IGLOO, ProASIC3, SmartFusion, Fusion, ProASICPLUS, ProASIC, Axcelerator, RTAX-S, eX, and SX-A

  5. Click Layoutin the Design Flow Window to place-and-route your design.
  6. Click Back-Annotate in the Design Flow Window. Choose SDF as CAE type and appropriate simulation language. Select Netlist in the Export Additional Files area and Click OK. If you are exporting files post-layout,

    Designer exports <top>_ba.vhd and <top>_ba.sdf to your Libero project. The “_ba” is added by Libero to identify these for back-annotation purposes. <top> is the top root name. Pre-layout exported files do not contain “_ba” and are exported simply as *.vhd and *.sdf. The files are visible in the Files tab, under Implementation Files.

  7. Click Programming File in the design flow tree if you wish to create a programming file for your design. This step can be performed later after you are satisfied with the back-annotated timing simulation.
  8. From the File menu, select Exit. Click Y es to save the design before closing Designer. Designer saves all of the design information in an *.adb file. The <project>.adb file is visible in the File Manger, in the Designer Views folder. To re-open this file at any time, simply double-click it.