8.4.1 Creating a Project Library in SpeedWave

If you use SpeedWave to simulate your designs, you must create a project library in SpeedWave, in addition to creating an Actel project in Project Manager, for each VHDL synthesis-based Actel project. The following procedures describe the process.

  1. Open the VHDL Manager from the simulation toolbox. This displays the HDL Manager window.
  2. Setup a project. Choose the Create command from the Library menu. The Create Library dialog box is displayed. Make sure the path in the Library Path box is correct and already exists. Type “user” in the Symbolic Name box and click OK. Make sure the Output window reports no errors in the Output window.
  3. Verify that the user library icon appears under the VHDL User Libraries section in the VHDL View window.
  4. Add the compiled Actel VITAL library to the Project Libraries. Choose the Add to Workspace command from the Library menu. The Add Existing Library to Workspace dialog box is displayed. Click the ellipsis box to open the Select Directory dialog box. Browse to the “c:\actel\lib\vtl\95\swave\<vhd_fam>.lib” directory and click OK. Click OK again in the Add Existing Library to Workspace dialog box. If you have not compiled the Actel VITAL library, go to Compiling Actel VITAL Libraries for the procedure.
    Note: Only add the <vhd_fam>.lib if you have referenced Actel cores in your VHDL netlist.
  5. Add system libraries to the Project Libraries. Make sure the SYNOPSYS.LIB and IEEE.LIB libraries are listed under VHDL System Libraries in the VHDL View window. If they are not present you must reinstall SpeedWave making sure to choose the Synopsys IEEE libraries when prompted.
  6. Save the project workspace. Choose the Save command from the File menu.