8.6 Actel-Innoveda Design Considerations

This chapter contains information to assist in creating Actel designs with the Innoveda eProduct Designer software. Topics include naming conventions, adding pins to the schematic, generating a top-level symbol, buried I/Os, adding power and ground, sheets and symbols, assigning pins in a schematic, adding SmartGen cores, adding FPGA Express blocks, generating an EDIF netlist, generating a structural VHDL netlist, using FPGA Express with SpeedWave, and using FPGA Express with ViewSim.