18.4.2 Naming Convention for FIFOs

FIFO model names consist of up to the following four parts:

A base name indicating the type and size (FIFO256x9)
A one character code designating the write port as asynchronous (A) or synchronous (S)
A one or two character code designating the read port as asynchronous (A) or synchronous registered (SR) or synchronous transparent (ST)
An optional one character code designating parity (P) generated

FIFO256x9SSRP is a 256-word by 9-bit FIFO with synchronous write and synchro-nous read ports (synchronous to separate clocks named RCLKS and WCLKS), has registered out-puts and uses the generate parity feature.

FIFO Interface Signals

This following figure and the table describe FIFO interface signals.

Table 18-270. FIFO Signal Descriptions
FIFO Signal	Bits	In/Out	Description
DI<8:0>	9	IN	Input data bits <8:0>, <8> can be used for parity in
LEVEL<7:0>	8	IN	Reference signal for the generation of the EQTH and GEQTH flags
LGDEP<2:0>	3	IN	Configures DEPTH of the FIFO to 2(LGDEP+1)
WRB	1	IN	Negative true write pulse
RDB	1	IN	Negative true read pulse
WBLKB	1	IN	Negative true write block select
RBLKB	1	IN	Negative true read block select
PARODD	1	IN	Selects odd parity generation/detect when high, even when low
WCLKS	1	IN	Write clock used in synchronous mode on write side
RCLKS	1	IN	Write clock used in synchronous mode on read side
RESET	1	IN	Negative true reset for FIFO pointers
DO<8:0>	9	OUT	Output data bits <8:0>, <8> can be used for parity out
FULL	2	OUT	FIFO flag. FULL prevents write. EMPTY prevents read
EMPTY	1	OUT	FIFO flag. EMPTY prevents read
WPE	1	OUT	Write parity error flag
RPE	1	OUT	Read parity error flag
EQTH	1	OUT	EQTH is true when the FIFO holds (LEVEL) words
GEQTH	1	OUT	GEQTH is true when the FIFO holds (LEVEL) words or more
DIS	1	IN	Signal used for memory cascade. Use ACTgen to generate the FIFO.
DOS	1	OUT	Signal used for memory cascade. Use ACTgen to generate the FIFO.

RAM256x9AA

This component is supported by A500K, APA families.

Figure 18-119. RAM256x9AA Logic Diagram

Function: Asynchronous Write/Asynchronous Read RAM with Parity Checking
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, PARROD, DIS
Output: DO, WPE, RPE, DOS

Table 18-271. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9AAP

This component is supported by A500K, APA families.

Figure 18-120. RAM256x9AAP Logic Diagram

Function: Asynchronous Write/Asynchronous Read RAM with Parity Generation
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, PARROD, DIS
Output: DO, DOS

Table 18-272. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9ASR

This component is supported by A500K, APA families.

Figure 18-121. RAM256x9ASR Logic Diagram

Function: Asynchronous Write/Synchronous Read RAM with Registered Output and Parity Checking
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, RCLKS, PARROD, DIS
Output: DO, WPE, RPE, DOS

Table 18-273. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9ASRP

This component is supported by A500K, APA families.

Figure 18-122. RAM256x9ASRP Logic Diagram

Function: Asynchronous Write/Synchronous Read RAM with Registered Output and Parity Generation
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, RCLKS, PARROD, DIS
Output: DO, DOS

Table 18-274. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9AST

This component is supported by A500K, APA families.

Figure 18-123. RAM256x9AST Logic Diagram

Function: Asynchronous Write/Synchronous Read RAM with Transparent Output and Parity Checking
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, RCLKS, PARROD, DIS
Output: DO, WPE, RPE, DOS

Table 18-275. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9ASTP

This component is supported by A500K, APA families.

Figure 18-124. RAM256x9ASTP Logic Diagram

Function: Asynchronous Write/Synchronous Read RAM with Transparent Output and Parity Generation
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, RCLKS, PARROD, DIS
Output: DO, DOS

Table 18-276. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9SA

This component is supported by A500K, APA families.

Figure 18-125. RAM256x9SA Logic Diagram

Function: Synchronous Write/Asynchronous Read RAM with Parity Checking
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, WCLKS, PARROD, DIS
Output: DO, WPE, RPE, DOS

Table 18-277. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9SAP

This component is supported by A500K, APA families.

Figure 18-126. RAM256x9SAP Logic Diagram

Function: Synchronous Write/Asynchronous Read RAM with Parity Generation
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, WCLKS, PARROD, DIS
Output: DO, DOS

Table 18-278. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9SSR

This component is supported by A500K, APA families.

Figure 18-127. RAM256x9SSR Logic Diagram

Function: Synchronous Write/Synchronous Read RAM with Registered Output and Parity Checking
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, PARROD, DIS
Output: DO, WPE, RPE, DOS

Table 18-279. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9SSRP

This component is supported by A500K, APA families.

Figure 18-128. RAM256x9SSRP Logic Diagram

Function: Synchronous Write/Synchronous Read RAM with Registered Output and Parity Generation
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, PARROD, DIS
Output: DO, DOS

Table 18-280. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9SST

This component is supported by A500K, APA families.

Figure 18-129. RAM256x9SST Logic Diagram

Function: Synchronous Write/Synchronous Read RAM with Transparent Output and Parity Checking
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, PARROD, DIS
Output: DO, WPE, RPE, DOS

Table 18-281. Tile Usage
Family	RAM Port Tiles
All listed	16

RAM256x9SSTP

This component is supported by A500K, APA families.

Figure 18-130. RAM256x9SSTP Logic Diagram

Function: Synchronous Write/Synchronous Read RAM with Transparent Output and Parity Generation
Input: DI, RADDR, WADDR, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, PARROD, DIS
Output: DO, DOS

Table 18-282. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9AA

This component is supported by A500K, APA families.

Figure 18-131. FIFO256x9AA Logic Diagram

Function: Asynchronous Write/Asynchronous Read FIFO with Parity Checking
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, WPE, RPE, EQTH, GEQTH, DOS

Table 18-283. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9AAP

This component is supported by A500K, APA families.

Figure 18-132. FIFO256x9AAP Logic Diagram

Function: Asynchronous Write/Asynchronous Read FIFO with Parity Generation
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, EQTH, GEQTH, DOS

Table 18-284. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9ASR

This component is supported by A500K, APA families.

Figure 18-133. FIFO256x9ASR Logic Diagram

Function: Asynchronous Write/Synchronous Read FIFO with Registered Output and Parity Checking
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, RCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, WPE, RPE, EQTH, GEQTH, DOS

Table 18-285. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9ASRP

This component is supported by A500K, APA families.

Figure 18-134. FIFO256x9ASRP Logic Diagram

Function: Asynchronous Write/Synchronous Read FIFO with Registered Output and Parity Generation
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, RCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, EQTH, GEQTH, DOS

Table 18-286. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9SA

This component is supported by A500K, APA families.

Figure 18-135. FIFO256x9SA Logic Diagram

Function: Synchronous Write/Asynchronous Read FIFO with Parity Checking
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, WCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, WPE, RPE, EQTH, GEQTH, DOS

Table 18-287. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9SAP

This component is supported by A500K, APA families.

Figure 18-136. FIFO256x9SAP Logic Diagram

Function: Synchronous Write/Asynchronous Read FIFO with Parity Generation
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, WCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, EQTH, GEQTH, DOS

Table 18-288. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9SSR

This component is supported by A500K, APA families.

Figure 18-137. FIFO256x9SSR Logic Diagram

Function: Synchronous Write/Synchronous Read FIFO with Registered Output and Parity Checking
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, WPE, RPE, EQTH, GEQTH, DOS

Table 18-289. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9SSRP

This component is supported by A500K, APA families.

Figure 18-138. FIFO256x9SSRP Logic Diagram

Function: Synchronous Write/Synchronous Read FIFO with Registered Output and Parity Generation
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, EQTH, GEQTH, DOS

Table 18-290. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9SST

This component is supported by A500K, APA families.

Figure 18-139. FIFO256x9SST Logic Diagram

Function: Synchronous Write/Synchronous Read FIFO with Transparent Output and Parity Checking
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, WPE, RPE, EQTH, GEQTH, DOS

Table 18-291. Tile Usage
Family	RAM Port Tiles
All listed	16

FIFO256x9SSTP

This component is supported by A500K, APA families.

Figure 18-140. FIFO256x9SSTP Logic Diagram

Function: Synchronous Write/Synchronous Read FIFO with Transparent Output and Parity Generation
Input: DI, LEVEL, LGDEP, WRB, RDB, WBLKB, RBLKB, WCLKS, RCLKS, RESET, PARROD, DIS
Output: DO, FULL, EMPTY, EQTH, GEQTH, DOS

Table 18-292. Tile Usage
Family	RAM Port Tiles
All listed	16

PLLMACRO

This component is supported by APA family.

Figure 18-141. PLLMACRO Logic Diagram

Function: Phase locked loop; please refer to PLL and APA datasheets for more information on the PLL.

Table 18-293. Tile Usage
Family	I/O Tiles
All listed	6

Rev: A