18.4.1 Naming Convention for RAMs
RAM model names consist of up to the following four parts:
- A base name indicating the type and size (RAM256x9)
- A one character code designating the write port as asynchronous (A) or synchronous (S)
- A one or two character code designating the read port as asynchronous (A) or synchronous registered (SR) or synchronous transparent (ST)
- An optional one character code designating parity (P) generated.
RAM256x9SAP is a 256-word by 9-bit RAM with synchronous write and asynchronous read ports using the generate parity feature.
SRAM Interface Signals
The following figure and the table describe basic embedded SRAM interface signals.
| SRAM Signal | Bits | In/Out | Description |
|---|---|---|---|
| DI<8:0> | 9 | IN | Input data bits <8:0>, <8> can be used for parity in |
| RADDR<7:0> | 8 | IN | Read address |
| WADDR<7:0> | 8 | IN | Write address |
| WRB | 1 | IN | Negative true write pulse |
| RDB | 1 | IN | Negative true read pulse |
| WBLKB | 1 | IN | Negative true write block select |
| RBLKB | 1 | IN | Negative true read block select |
| PARODD | 1 | IN | Selects odd parity generation/detect when high, even when low |
| WCLKS | 1 | IN | Write clock used in synchronous mode on write side |
| RCLKS | 1 | IN | Write clock used in synchronous mode on read side |
| DO<8:0> | 9 | OUT | Output data bits <8:0>, <8> can be used for parity out |
| WPE | 1 | OUT | Write parity error flag |
| RPE | 1 | OUT | Read parity error flag |
| DIS | 1 | IN | Signal used for memory cascade. Use ACTgen to generate the RAM block. |
| DOS | 1 | OUT | Signal used for memory cascade. Use ACTgen to generate the RAM block |