9.2 Supported Families
Microchip®’s Libero® Integrated Design Environment (IDE) and Designer software support the following device families:
- IGLOO®
- ProASIC3
- SmartFusion
- Fusion
- ProASICPLUS
- ProASIC
- Axcelerator
- eX
- SX-A
- MX
- RTAX-S/SL
- RTSX-SU
When a family name is specified, it refers to the device family and all of its derivatives, unless otherwise noted. The following table lists the supported device families and their derivatives.
| Device Family | Family Derivatives | Description |
|---|---|---|
| IGLOO® | IGLOO | The ultra‑low‑power, programmable solution |
| IGLOOe | Higher‑density IGLOO FPGAs with six PLLs and additional I/O standards | |
| IGLOO nano | The industry’s lowest‑power, smallest‑size solution | |
| IGLOO PLUS | Low‑power FPGAs with enhanced I/O capabilities | |
| ProASIC3 | ProASIC3 | Low‑power, low‑cost FPGA solution |
| ProASIC3E | Higher‑density ProASIC3 FPGAs with six PLLs and additional I/O standards | |
| ProASIC3 nano | Lowest‑cost solution with enhanced I/O capabilities | |
| ProASIC3L | FPGA family balancing low power, performance, and cost | |
| Automotive ProASIC3 | ProASIC3 FPGAs qualified for automotive applications | |
| Military ProASIC3/EL | Military‑temperature devices including A3PE600L, A3P1000, and A3PE3000L | |
| RT ProASIC3 | Radiation‑tolerant RT3PE600L and RT3PE3000L devices | |
| SmartFusion | SmartFusion | Intelligent mixed‑signal FPGAs integrating an FPGA, an ARM® Cortex‑M3 processor, and programmable analog, providing full customization and IP protection |
| Fusion | Fusion | Mixed‑signal FPGAs integrating ProASIC3 FPGA fabric, programmable analog, support for ARM® Cortex‑M1 soft processors, and flash memory in a single device |
| ProASICPLUS | ProASICPLUS | Second‑generation, high‑density programmable flash devices with ASIC‑style capabilities in a single‑chip solution (75k to 1M gates) |
| ProASIC | ProASIC | This family has been discontinued and is not recommended for new designs |
| Axcelerator | Axcelerator | Nonvolatile, high‑speed antifuse FPGAs with FuseLock™ design security and an embedded FIFO controller (125k to 2M gates) |
| eX | eX | Third‑generation, low‑power, low‑density antifuse devices based on the SX‑A architecture, supporting system performance greater than 350 MHz (3k to 12k gates) |
| SX‑A | SX‑A | Antifuse devices with 270 MHz system performance and a sea‑of‑modules architecture enabled by patented metal‑to‑metal antifuse interconnect technology (12k to 108k gates) |
| MX | MX | Antifuse devices with 250 MHz system performance and MultiPlex I/O architecture, supporting mixed‑voltage systems and operation at 5.0V (3k to 54k gates) |
| RTAX‑S/SL | RTAX‑S/SL | Radiation‑tolerant antifuse‑based FPGAs designed for space applications, supporting system performance greater than 350 MHz (250k to 4M system gates) |
| RTSX‑SU | RTSX‑SU | Radiation‑tolerant antifuse‑based FPGAs with 250 MHz system performance (48k to 108k system gates) |