7.6.1 Behavioral Simulation

Use the following procedure to perform a behavioral simulation of an Actel design:

Note: When installing the Innoveda SpeedWave simulator, you have the option of installing a standard IEEE library or the Synopsys version.You must install the Synopsys libraries for compatibility with Actel VITAL libraries and you must include the Synopsys library in your invocations. The commands in this guide use the Synopsys version of the IEEE libraries.

Create a working directory. Type the vanlibcreate ./user.lib user command at the prompt.
Create a soft link to the synthesis library. Type the following command at the prompt:
```
ln -s $VANTAGE_VSS/pgm/libs/synopsys.lib synopsys
```

Analyze your behavioral VHDL design files and testbench. Type the following commands at the prompt:

analyze -src <design_name>.vhd -lib user.lib -libieee -lib synopsys
analyze -src <vhdl_test_bench>.vhd -lib user.lib -libieee
-lib synopsys

Map to the Actel VITAL and FPGA libraries. If any Actel cores are instantiated in your VHDL source, you must add the following switches when analyzing your VHDL design files:
```
analyze -src <design_name>.vhd -lib user.lib -lib $ALSDIR/lib/vtl/95/
swave/<vhd_fam> -libieee -lib synopsys
```
Add the following lines to your VHDL design files to reference the Actel Family library in your VHDL design files:
```
library <vhd_fam>;
use <vhd_fam>.components.all;
```
Simulate your design. Type the following command at the prompt:
```
vbsim -cfg <configuration_name> -until complete -lib user.lib -libieee -lib synopsys
```
If any Actel cores are instantiated in your VHDL source, you must simulate using the compiled Actel VHDL library for that family. For example, to simulate a configuration named cfg_tb_behavior for a MX device, type the following command at the prompt:
```
vbsim -cfg cfg_tb_behavior -until complete -lib user.lib
-libieee -lib synopsys -lib $ALSDIR/lib/vtl/95/swave/a40mx
```

For more information about performing simulation with SpeedWave, see the Innoveda documentation.