7.6.2 Structural Simulation

Use the following procedure to perform a structural simulation of an Actel design:

Synthesize your design. Refer to the documentation included with your synthesis tool for information about synthesis.
Analyze the structural VHDL netlist and the testbench. If you have not already generated a structural VHDL netlist, go to Generating a Structural VHDL Netlist for the procedure. Type the following commands at the prompt to analyze the VHDL netlist and testbench:
```
analyze -src <design_name>.vhd -lib user.lib -lib $ALSDIR/lib/vtl/95/
swave/<vhd_fam> -libieee -lib synopsys
```
```
analyze -src <vhdl_test_bench>.vhd -lib user.lib -lib $ALSDIR/lib/vtl/
95/swave/<vhd_fam> -libieee -lib synopsys
```
Simulate your design. Type the following command at the prompt:
```
vbsim -cfg <configuration_name> -until complete
-lib user.lib -libieee -lib synopsys -lib $ALSDIR/lib/vtl/95/swave/
<vhd_fam>
```
For example, to simulate a configuration named cfg_tb_structure for a 40MX device, type the following command at the prompt:
```
vbsim -cfg cfg_tb_structure -until complete -lib user.lib -libieee -lib
synopsys -lib $ALSDIR/lib/vtl/95/swave/a40mx
```

For more information about performing simulation with SpeedWave, see the Innoveda documentation.