24.1 Document Organization

The Verilog Simulation Guide contains the following chapters:

Chapter 1 - Setup contains information about setting up Verilog libraries for use in simulating Microchip designs.

Chapter 2 - Design Flow illustrates and describes the design flow for simulating Microchip designs using Verilog Simulation tools.

Chapter 3 - Generating Netlists contains information for generating EDIF and structural Verilog netlists.

Chapter 4 - Interpreted Simulation describes the procedures for performing functional (behavioral and structural) and timing simulation on an Microchip design using tools that either interpret library and design files, or compile them on-the-fly.

Chapter 5 - Simulation with ModelSim describes the procedures for performing functional (behavioral and structural) and timing simulation on an Microchip design using commands for the ModelSim simulator.