24.1.3.2 NC-Verilog

Use the following procedure to compile libraries for the Cadence NC-Verilog simulator. This procedure compiles an Microchip verilog library in the “$ALSDIR/lib/vlog/ncvlog” directory. You must compile the FPGA library models for the Microchip verilog libraries to function properly.

1. Create a directory called “ncvlog” in the “$ALSDIR/lib/vlog” directory.
2. Change to the “$ALSDIR/lib/vlog/ncvlog” directory.
3. Create a directory named <act_fam>.
4. Map the library. Compile the models and create the “cds.lib” file as follows:

   INCLUDE $CDS/tools/inca/files/cds.lib

   DEFINE <vhd_fam> $ALSDIR/lib/vlog/ncvlog/<act_fam>

5. Compile the library. Type the following command at the prompt:

   ncvlog -work <act_fam> -messages $ALSDIR/lib/vlog/<act_fam>.vhd

   For example, to compile the 40MX library for your simulator, type the following command:

   ncvlog -work 40mx -messages $ALSDIR/lib/vlog/40mx.v

6. (Optional) Compile the migration library. Only perform this step if you are using the migration library. Type the following command at the prompt:

   ncvlog -work <act_fam> -messages $ALSDIR/lib/vlog/<act_fam>_mig.v