MPLAB® Harmony 3 Class B Library for SAM E5x/D5x Devices

1 MPLAB® Harmony 3 Class B Library for SAM E5x/D5x Devices

1.1 Class B Peripheral Library Introduction

1.2 Class B Peripheral Library Usage

1.3 Configuring the Library

1.4 SAM E5x D5x Class B API Usage Example

1.5 Class B Library Interface

2 List of Constants

2.1 CLASSB_RESULT_ADDR

2.2 CLASSB_COMPL_RESULT_ADDR

2.3 CLASSB_ONGOING_TEST_VAR_ADDR

2.4 CLASSB_TEST_IN_PROG_VAR_ADDR

2.5 CLASSB_WDT_TEST_IN_PROG_VAR_ADDR

2.6 CLASSB_FLASH_TEST_VAR_ADDR

2.7 CLASSB_INTERRUPT_TEST_VAR_ADDR

2.8 CLASSB_INTERRUPT_COUNT_VAR_ADDR

2.9 CLASSB_SRAM_STARTUP_TEST_SIZE

2.10 CLASSB_CLOCK_ERROR_PERCENT

2.11 CLASSB_CLOCK_RTC_CLK_FREQ

2.12 CLASSB_CLOCK_TEST_RTC_CYCLES

2.13 CLASSB_CLOCK_TEST_RTC_RATIO_NS

2.14 CLASSB_CLOCK_TEST_RATIO_NS_MS

2.15 CLASSB_CLOCK_DEFAULT_CLOCK_FREQ

2.16 CLASSB_INVALID_TEST_ID

2.17 CLASSB_CLOCK_MAX_CLOCK_FREQ

2.18 CLASSB_CLOCK_MAX_SYSTICK_VAL

2.19 CLASSB_CLOCK_MAX_TEST_ACCURACY

2.20 CLASSB_CLOCK_MUL_FACTOR

2.21 CLASSB_FLASH_CRC32_POLYNOMIAL

2.22 CLASSB_SRAM_TEST_BUFFER_SIZE

2.23 CLASSB_SRAM_APP_AREA_START

2.24 CLASSB_SRAM_FINAL_WORD_ADDRESS

2.25 CLASSB_SRAM_BUFF_START_ADDRESS

2.26 CLASSB_SRAM_TEMP_STACK_ADDRESS

2.27 CLASSB_SRAM_ALL_32BITS_HIGH

2.28 CLASSB_INTR_DEVICE_VECT_OFFSET

2.29 CLASSB_INTR_VECTOR_TABLE_SIZE

2.30 CLASSB_INTR_MAX_INT_COUNT

2.31 CLASSB_INTR_TEST_RTC_COUNT

2.32 CLASSB_INTR_TEST_TC_COUNT

3 List of Data Types

3.1 CLASSB_TEST_ID

3.2 CLASSB_TEST_STATUS

3.3 CLASSB_TEST_STATE

3.4 CLASSB_INIT_STATUS

3.5 CLASSB_STARTUP_STATUS

3.6 CLASSB_TEST_TYPE

3.7 CLASSB_SST_RESULT_BF

3.8 CLASSB_RST_RESULT_BF

3.9 CLASSB_SRAM_MARCH_ALGO

3.10 CLASSB_PORT_INDEX

3.11 CLASSB_PORT_PIN

3.12 CLASSB_PORT_PIN_STATE

3.13 CLASSB_CPU_PC_TEST_VALUES

4 List of Interface Routines

4.1 CLASSB_ClearTestResults

4.2 CLASSB_GetTestResult

4.3 CLASSB_TestWDT

4.4 CLASSB_GlobalsInit

4.5 CLASSB_Init

4.6 CLASSB_Startup_Tests

4.7 CLASSB_SST_WDT_Recovery

4.8 CLASSB_App_WDT_Recovery

4.9 CLASSB_SelfTest_FailSafe

4.10 CLASSB_CPU_RegistersTest

4.11 CLASSB_FPU_RegistersTest

4.12 CLASSB_CPU_PCTest

4.13 CLASSB_FlashCRCGenerate

4.14 CLASSB_FlashCRCTest

4.15 CLASSB_SRAM_MarchTestInit

4.16 CLASSB_ClockTest

4.17 CLASSB_SST_InterruptTest

4.18 CLASSB_RST_IOTest

4.19 CLASSB_IO_InputSamplingEnable

Microchip Information

Microchip Devices Code Protection Feature