3.10.1 AVR Controller Sub-System Overview

The following figure shows a block diagram of the ATA8510/15. The AVR controller sub-system consists of the AVR CPU core, its program memory and a data bus with data memory and peripheral blocks attached. The receive path and the transmit path also have their user interfaces connected to the data bus.

Figure 3-46. AVR Controller Sub-System Overview

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.