3.10.9 CRC

An 8-bit CRC generator with byte access is provided as a standard AVR peripheral module. The CRC module is not supported by the ATA8510/15 firmware but it is available for use by customer application software, for example, to verify the validity of memory data. This CRC generator is not intended to be used to check the received and transmitted telegrams as there are more flexible CRC modules available in the RX and TX data path of the ATA8510/15.

Key properties:

  • Very fast parallel CRC computation
  • Accessible via AVR bus
  • Fixed polynomial

Generally, CRC checkers detect the following types of errors:

  1. Single-bit errors
  2. Two-bit errors
  3. Three-bit and other odd-number-bit errors
  4. Burst errors that are less than or equal to the CRC length
  5. Most burst errors that are greater than the CRC length
  6. The types of errors that CRC checker detects depending on the generator polynomial

The implemented CRC checker is using the following polynomial: CRC(x) = x^8 + x^2 + x^1 + 1.

Figure 3-92. CRC Equivalent Block Diagram

The parallel implementation of the polynomial is equivalent to the linear feedback shift register (LFSR), as shown in the preceding figure. The initial value of the 8-bit CRC data register is 0x00. With some standards, the data is expected to enter the processor LSBF (least significant bit first). In this case, the incoming data and the resulting CRC must be bit reflected. A binary number is reflected by swapping all of its bits around the central point. For example, 1101 is the reflection of 1011. The bits REFLI and REFLO of the CRC control register are required to configure the bit order of incoming and outgoing data. If REFLI is FALSE (initial value), input bytes are processed with bit 7 being treated as the most significant bit (MSB) and bit 0 being treated as the least significant bit (LSB). If REFLI is TRUE, each byte is reflected before being processed. If REFLO is set to FALSE (initial value), the final value in the CRC register is fed into the output stage directly; otherwise, if this parameter is TRUE, the final CRC register value is reflected first.

CRC computation:

  1. Initialize the CRC data register
  2. Write message byte to CRC data register
  3. Continue with step 2 until there are no message bytes left
  4. Read CRC data register
  5. Continue with step 1