3.10.8 SPI – Serial Peripheral Interface

The serial peripheral interface (SPI) allows for a synchronous data transfer between the ATA8510/15 and peripheral devices or external microcontrollers. The SPI includes the following features:

• Full-duplex, three-wire synchronous data transfer
• Host or client operation
• LSB first or MSB first data transfer
• Programmable bit rates
• 4 bytes receive buffer, 4 bytes transmit buffer
• EOT interrupt flag
• Configurable fill status interrupt flags
• Wake-up from idle mode
• Double speed (CK/2) host SPI mode

The SPI interface is also used for program memory and EEPROM downloading or uploading. See In-System Programming for serial in-system programming (ISP).

The interconnection between host and client CPUs with SPI is shown in the preceding figure. The system consists of two shift registers and a host clock generator. The SPI host initiates the communication cycle when pulling low the low active client select (NSS) pin of the desired client. Host and client prepare the data to be sent in their respective shift registers. Additionally, the host generates the required clock pulses on the SCK line to interchange data. Data is always shifted from host to client on the host out/client in (MOSI) line and from client to host on the host in/client out (MISO) line. After each data packet, for example, a telegram or any number of data bytes forming a packet, the host synchronizes the client by pulling high the NSS line.

When configured as a host, the SPI interface has no automatic control of the NSS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI data register starts the SPI clock generator, and the hardware shifts the 8 bits into the client. After shifting one byte, the next byte is fetched from the transmit buffer. If it is empty, the SPI clock generator stops. The host may continue to shift the next byte by writing it into SPDR or signal the end of packet by pulling high the NSS line. The last incoming bytes are kept in the receive buffer for later use.

When configured as a client, the SPI interface remains sleeping with MISO tri-stated as long as the NSS pin is driven high. In this state, firmware may fill the transmit buffer through the SPI data register (SPDR), but the data is not shifted out by incoming clock pulses on the SCK pin until the NSS pin is driven low. As one byte was completely shifted, the end of transmission flag (SPIF) is set. If the SPI interrupt enable bit, SPIE, in the SPCR register is set, an interrupt is requested.

This can be used for byte-wise transmission when the 4-byte receive and transmit buffers are not used.

As shown in the preceding figure, the system is buffered independently in the transmit direction and the receive direction. Both buffers are accessed by firmware through the SPDR register. The transmit buffer can be completely filled by the firmware. If the buffer is empty when a new byte is to be transferred to the shift register, the latest data are sent multiple times. The transmit buffer state can be controlled by the fill status (TFL) and the corresponding fill status interrupt (TXIF).

The receive buffer can be read as long as it contains data. If it is empty, the latest byte is repeated. If the receive buffer is full and a new complete byte is received before the buffer is read, the oldest data in the buffer gets lost. The new byte is transferred from the shift register into the receive buffer in any case. The receive buffer state can be controlled by the fill status (RFL) and the corresponding fill status interrupt (RXIF).

In SPI client mode, the control logic samples the incoming signal of the SCK pin. To ensure correct sampling of the clock signal the minimum low and high period must be:

Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK and NSS pins are overridden according to the following table. For more details on automatic port overrides, refer to Alternate Port Functions.