3.10.4 System Clock and Clock Options

The following figure presents the principal clock systems in the AVR and their distribution. Not all of the clocks need to be active at a given time. To reduce power consumption, the clocks to modules not being used can be stopped by using different sleep modes, as described in Sleep Modes and Active Power Reduction. Fine-grained clock gating can be performed by using the power reduction registers (PRR0, PRR1 and PRR2). Additional power reduction bits are available for the RX DSP (RDPR) and TX DSP (TDEN).

The AVR clock management supports the switching of the AVR clock source during operation. This allows for a start-up with the fast RC oscillator (CLK_FRC) and then switching to the more accurate XTO based clock (CLK_XTO4, CLK_XTO6) used as the system clock (CLK_SYS).