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ATA8510
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3
Hardware
3.10
AVR Controller
3.10.2
CPU Core
Features
1
General Product Description
2
System Functional Description
3
Hardware
3.1
Overview
3.2
Crystal Oscillator
3.3
Fractional-N PLL
3.4
Receive Path
3.5
Transmit Path
3.6
Data and Support FIFOs
3.7
SPDT RF Switch and Automatic Antenna Tuning
3.8
RF Front-End Register Description
3.9
Sequencer State Machine
3.10
AVR Controller
3.10.1
AVR Controller Sub-System Overview
3.10.2
CPU Core
3.10.2.1
Architectural Overview
3.10.2.2
ALU
3.10.2.3
Status Register
3.10.2.4
General Purpose Register File
3.10.2.5
Stack Pointer
3.10.2.6
Instruction Execution Timing
3.10.2.7
Reset and Interrupt Handling
3.10.3
Memories
3.10.4
System Clock and Clock Options
3.10.5
Sleep Modes and Active Power Reduction
3.10.6
I/O Ports
3.10.7
Timer Module
3.10.8
SPI – Serial Peripheral Interface
3.10.9
CRC
3.10.10
debugWIRE – On-Chip Debug System
3.10.11
Memory Access via SPM/LPM
3.10.12
Memory Programming
3.10.13
Specific Interrupts Handling
3.10.14
External Interrupts
3.11
Power Management
4
Application
5
Electrical Characteristics
6
Timing Characteristics
7
Appendix
8
Ordering Information
9
Package Information
10
Document Revision History
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3.10.2 CPU Core
