3.11.6.2 SUPFR – Supply
Interrupt Flag Register
| Name: | SUPFR |
| Offset: | 0x0CA |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | AVCCLF | AVCCRF | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved for
future use and reads as ‘0’.
Bit 6 – Reserved
Bit
This bit is reserved for
future use and reads as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved for
future use and reads as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved for
future use and reads as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved for
future use and reads as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved for
future use and reads as ‘0’.
Bit 1 – AVCCLF AVCC Low Interrupt
Flag
This flag is set if the AVCC
level falls below the lowest limit of the operating range of the analog circuits in
the RF front end and XTO. The circuits are disabled. The settling procedure of the
circuits must, thus, be performed again before valid data can be processed. If the
I-bit in SREG is set to ‘1’, the AVCCLM bit in the SUPCR register
is set to ‘1’, sysEventConf.AVCCLOWM is set to ‘1’
and the AVR then jumps to the corresponding interrupt vector. The flag is cleared
when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical ‘1’ to its bit location.
Bit 0 – AVCCRF AVCC Reset Interrupt Flag
This bit is set if an AVCC
reset occurs. When AVCC is turned off or falls below the reset threshold during
operation, the AVCCRF flag is set. In this case, the operation of the RF front end
and XTO is stopped by the hardware reset and the digital settings of the RF front
end and XTO are lost.
