3.11.6.3 MCUSR – MCU Status Register

Name: MCUSR
Offset: 0x02B
Reset: 0x00

The MCU status register provides the information on which reset source caused an AVR reset. PORF, EXTRF and WDRF trigger the non-maskable reset interrupt.

Bit 76543210 
 WDRFEXTRFPORF 
Access RRRRR/WRR/WR/W 
Reset 00000000 

Bit 7 –  Reserved Bit

This bit is reserved for future use and read as ‘0’.

Bit 6 –  Reserved Bit

This bit is reserved for future use and read as ‘0’.

Bit 5 –  Reserved Bit

This bit is reserved for future use and read as ‘0’.

Bit 4 –  Reserved Bit

This bit is reserved for future use and read as ‘0’.

Bit 3 – WDRF Watchdog Reset Flag

This bit is set if a watchdog reset occurs. The bit is cleared by a power-on reset or by writing a logic ‘0’ to the flag.

Bit 2 –  Reserved Bit

This bit is reserved for future use and read as ‘0’.

Bit 1 – EXTRF External Reset Flag

This bit is set if an external reset occurs. The bit is cleared by a power-on reset or by writing a logic ‘0’ to the flag.

Bit 0 – PORF Power-On Reset Flag

This bit is set if a power-on reset or a brown-out reset occurs due to a low DVCC voltage. The brown-out circuit is always active when the DVCC voltage is enabled. The bit is cleared only by writing a logic ‘0’ to the flag. To use the reset flags for identifying a reset condition, the user must read, then reset the MCUSR in a customer-defined program as soon as possible. If the register is cleared before another reset occurs, the source of the reset is found by examining the reset flags.