3.11.6.1 SUPCR – Supply
Control Register
| Name: | SUPCR |
| Offset: | 0x0CB |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | AVDIC | AVEN | DVDIS | | PVEN | AVCCLM | AVCCRM | |
| Access | R | R/W | R/W | R/W | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved for
future use and read as ‘1’.
Bit 6 – AVDIC AVCC Double
Internal Current
The internal bias current of
the AVCC regulator is increased if this bit is set to ‘1’. Higher
bias current provides more AVCC stability on fast load transitions. It is
automatically activated by firmware for the TX Mode when FEPAC > 0x2B. The
register must be ‘0’ in all other cases.
Bit 5 – AVEN AVCC
Enable
The RF front end and XTO power
supply providing AVCC is enabled by setting this bit. The bit is set automatically
if IDLEMode(XTO), RXMode or TXMode are started. Clearing this bit disables the AVCC
power supply and enables a reset of the RF front end and the
XTO.
Bit 4 – DVDIS DVCC Disable
The digital power supply is
disabled when setting this bit under the condition that no NPWRONx =
0 or PWRON = 1 pin is currently set. In
addition, the AVR switches to the reset state and the ATA8510/15 switches to OFFMode. The
digital power supply is enabled again using the PWRON and NPWRONx pins, which are
controlled externally.
Bit 3 – Reserved Bit
This bit is reserved for
future use and read as ‘0’.
Bit 2 – PVEN Power Amplifier Voltage Supply Enable
The internal supply voltage
for the power amplifier is enabled if this bit is set to ‘1’ and
the AVCC voltage regulator is working (SUPCR.AVEN = 1). Use the
VS_PA power supply in 5V Application mode.
Bit 1 – AVCCLM AVCC Low Interrupt Mask Bit
When the AVCCLM bit and the
I-bit in the AVR status register are set to ‘1’, the AVCC low
interrupt is enabled. The corresponding interrupt is executed if the AVCC voltage
falls below the AVCC low threshold, which is typically 100 mV below the nominal AVCC
voltage.
Bit 0 – AVCCRM AVCC Reset Interrupt Mask Bit
This bit is reserved for
future use and read as ‘0’.
