26.5.10.3 ECC Processing Upon Reads

When performing a 8/16/32-bit read, the matching 64-bit section + 8 ECC bits are read in memory and the ECC syndrome is computed on the 72-bit vector. Three cases can occur:

• No error is detected: the 8/16/32-bit read word is provided as is
• One error is found:
  • The error is corrected on the fly and the corrected word is provided seamlessly (the corrected word is not written back in the memory)
  • ECCCTRL.SECCNT is decremented (until reaching 0)
  • if ECCCTRL.SECCNT = 0, INTFLAG.SERR is set and an interrupt is triggered (if enabled)
• Two errors are found:
  • INTFLAG.DERR and INTFLAG.SERR are both set and an interrupt is triggered (if enabled)
  • The host which tried to read the faulty word receives a bus client error and the corrupted word.
  • Note: A bit error in the address field cannot be detected nor corrected.

The ECC feature is enabled by default after reset and can be disabled by setting ECCCTRL.ECCDIS (for the main array) and/or ECCCTRL.ECCDFDIS (for the Data Flash). Once disabled, it cannot be re-enabled manually, and will only be re-enabled automatically after the next reset. As long as the ECC feature is enabled, all SEC errors will be by default detected and corrected on the fly, whatever the configuration of the different NVMCTRL registers, and even if interrupts are pending.

For identifying a large amount of SEC errors being corrected, it is possible to configure ECCCTRL.SECCNT to any non-zero value. The counter will decrement upon each SEC error until reaching zero. Then, the INTFLAG.SERR will be set and an interrupt issued (if enabled). The counter must then be reloaded manually.