26.5.10.4 Fault Injection and Fault Capture
For functional safety, the ECC feature can be tested through the fault injection logic. This logic applies on top of the existing ECC logic which continues to work independently and allows corrupting (by flipping on purpose) 1 or 2 bits in the 72-bit vector (64-bit data + 8-bit ECC) at a specific address, upon reads or writes at this address in the memory, and capturing error details.
The following figure represents a subset of the fault injection and capture logic (the address bus and page buffer logic are not represented).
The selection of the fault injection mode (upon reads or writes, single or double error) is done in FLTCTRL.FLTMD. The address of the word to corrupt must be defined in FFLTADR.FLTADR. Only reads and writes to this specific address will affect the fault injection and capture logic.
The selection of the first bit to corrupt is done in FFLTPTR.FLT1PTR. If a second bit needs to be corrupted, it is selected in FFLTPTR.FLT2PTR. The following table explains which FLTxPTR value corresponds to which 64 data bits and 8 ECC bits:
| FFLTPTR.FLTxPTR Value | DATA BITS [0:63] | ECC Parity BITS [0:7] |
|---|---|---|
| 0x0 | -- | 0 |
| 0x1 | -- | 1 |
| 0x2 | -- | 2 |
| 0x3 | 0 | -- |
| 0x4 | -- | 3 |
| 0x5 to 0x7 | 1 to 3 | -- |
| 0x8 | -- | 4 |
| 0x9 to 0xF | 4 to 10 | -- |
| 0x10 | -- | 5 |
| 0x11 to 0x1F | 11 to 25 | -- |
| 0x20 | -- | 6 |
| 0x21 to 0x3F | 26 to 56 | -- |
| 0x40 | -- | 7 |
| 0x41 to 0x47 | 57 to 63 | -- |
| 0x48 to 0xFF | -- | -- |
The fault injection or capture is enabled when setting FLTCTRL.FLTEN.