35.7.22 Channel x Compare/Capture Buffer Value
CCBUFx is copied into CCx at TCC update time or CTRLBSET.CMD = UPDATE command when CTRLBSET.LUPD is 1.
Note: This register is
write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete. This register must be written with 32 bits accesses
only (no 8 or 16 bits writes).
Name: | CCBUFx |
Offset: | 0x70 + x*0x04 [x=0..3] |
Reset: | 0x00000000 |
Property: | Write-Synchronized |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CCBUF[17:10] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CCBUF[9:2] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CCBUF[1:0] | DITHERBUF[5:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23:6 – CCBUF[17:0] Channel x Compare/Capture Buffer Value
These bits hold the value of the Channel x Compare/Capture Buffer Value register. The register serves as the buffer for the associated Compare or Capture registers (CCx). Accessing this register using the CPU or DMA will affect the corresponding CCBUFVx status bit.
Note: When the TCC is configured as
16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB
of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION | Bits [23:m] |
---|---|
0x0 - NONE | 23:0 |
0x1 - DITH4 | 23:4 |
0x2 - DITH5 | 23:5 |
0x3 - DITH6 | 23:6 (depicted) |
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
Note: This bit field consists of the n
LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION | Bits [n:0] |
---|---|
0x0 - NONE | - |
0x1 - DITH4 | 3:0 |
0x2 - DITH5 | 4:0 |
0x3 - DITH6 | 5:0 (depicted) |