24.6.19 Channel Control B

This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits

Bit 3130292827262524 
       CMD[1:0] 
Access R/WR/W 
Reset 00 
Bit 2322212019181716 
 TRIGACT[1:0]       
Access R/WR/W 
Reset 00 
Bit 15141312111098 
   TRIGSRC[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
  LVL[1:0]EVOEEVIEEVACT[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 25:24 – CMD[1:0] Software Command

These bits define the software commands. Refer to Channel Suspend and Channel Resume and Next Suspend Skip.

Note: This bit field is not enable-protected.
CMD[1:0]NameDescription
0x0NOACTNo action
0x1SUSPENDChannel suspend operation
0x2RESUMEChannel resume operation
0x3-Reserved

Bits 23:22 – TRIGACT[1:0] Trigger Action

These bits define the trigger action used for a transfer.

Note: This bit field is enable-protected.
TRIGACT[1:0]NameDescription
0x0BLOCKOne trigger required for each block transfer
0x1-Reserved
0x2BEATOne trigger required for each beat transfer
0x3TRANSACTIONOne trigger required for each transaction

Bits 13:8 – TRIGSRC[5:0] Trigger Source

These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.
Note: This bit field is enable-protected.
Table 24-2. Peripheral Trigger Source (1)
ValueNameDescription
0x00DISABLEOnly software/event triggers
0x01ReservedReserved
0x02SERCOM0 RXSERCOM0 RX Trigger
0x03SERCOM0 TXSERCOM0TX Trigger
0x04SERCOM1 RX SERCOM1 RX Trigger
0x05SERCOM1 TXSERCOM1 TX Trigger
0x06SERCOM2 RXSERCOM2 RX Trigger
0x07SERCOM2 TXSERCOM2 TX Trigger
0x08SERCOM3 RXSERCOM3 RX Trigger
0x09SERCOM3 TXSERCOM3 TX Trigger
0x0ASERCOM4 RXSERCOM4 RX Trigger
0x0BSERCOM4 TXSERCOM4 TX Trigger
0x0CSERCOM5 RXSERCOM5 RX Trigger
0x0DSERCOM5 TXSERCOM5 TX Trigger
0x0ECAN0 RXCAN0 RX Trigger
0x0FCAN1 RXCAN1 RX Trigger
0x10TCC0 OVFTCC0 Overflow Trigger
0x11TCC0 MC0TCC0 Match/Compare 0 Trigger
0x12TCC0 MC1TCC0 Match/Compare 1 Trigger
0x13TCC0 MC2TCC0 Match/Compare 2 Trigger
0x14TCC0 MC3TCC0 Match/Compare 3 Trigger
0x15TCC1 OVFTCC1 Overflow Trigger
0x16TCC1 MC0TCC1 Match/Compare 0 Trigger
0x17TCC1 MC1TCC1 Match/Compare 1 Trigger
0x18TCC2 OVFTCC2 Overflow Trigger
0x19TCC2 MC0TCC2 Match/Compare 0 Trigger
0x1ATCC2 MC1TCC2 Match/Compare 1 Trigger
0x1BTC0 OVFTC0 Overflow Trigger
0x1CTC0 MC0TC0 Match/Compare 0 Trigger
0x1DTC0 MC1TC0 Match/Compare 1 Trigger
0x1ETC1 OVFTC1 Overflow Trigger
0x1FTC1 MC0TC1 Match/Compare 0 Trigger
0x20TC1 MC1TC1 Match/Compare 1 Trigger
0x21TC2 OVFTC2 Overflow Trigger
0x22TC2 MC0TC2 Match/Compare 0 Trigger
0x23TC2 MC1TC2 Match/Compare 1 Trigger
0x24TC3 OVFTC3 Overflow Trigger
0x25TC3 MC0TC3 Match/Compare 0 Trigger
0x26TC3 MC1TC3 Match/Compare 1 Trigger
0x27TC4 OVFTC4 Overflow Trigger
0x28TC4 MC0TC4 Match/Compare 0 Trigger
0x29TC4 MC1TC4 Match/Compare 1 Trigger
0x2AADC0 RESRDYADC0 Result Ready Trigger
0x2BADC1 RESRDYADC1 Result Ready Trigger
0x2CReservedReserved
0x2DDAC EMPTYDAC Empty Trigger
0x2EPTC EOCPTC End of Conversion Trigger
0x2FPTC WCOMPPTC Window Compare Trigger
0x30PTC SEQPTC Sequence Trigger
0x31SERCOM6 RXSERCOM6 RX Trigger
0x32SERCOM6 TXSERCOM6 TX Trigger
0x33SERCOM7 RXSERCOM6 RX Trigger
0x34SERCOM7 TXSERCOM6 TX Trigger
0x35TC5 OVFTC5 Overflow Trigger
0x36TC5 MC0TC5 Match/Compare 0 Trigger
0x37TC5 MC1TC5 Match/Compare 1 Trigger
0x38TC6 OVFTC6 Overflow Trigger
0x39TC6 MC0TC6 Match/Compare 0 Trigger
0x3ATC6 MC1TC6 Match/Compare 1 Trigger
0x3BTC7 OVFTC7 Overflow Trigger
0x3CTC7 MC0TC7 Match/Compare 0 Trigger
0x3DTC7 MC1TC7 Match/Compare 1 Trigger
0x3E-0x3FReservedReserved
Note:
  1. Refer to the Configuration Summary chapter for the list of peripherals and peripheral instances present in each variant.

Bits 6:5 – LVL[1:0] Channel Arbitration Level

These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For further details on arbitration schemes, refer to Arbitration.

Note: This bit field is not enable-protected.
TRIGACT[1:0]NameDescription
0x0LVL0Channel Priority Level 0
0x1LVL1Channel Priority Level 1
0x2LVL2Channel Priority Level 2
0x3LVL3Channel Priority Level 3

Bit 4 – EVOE Channel Event Output Enable

This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).

This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

Note: This bit is enable-protected.
ValueDescription
0Channel event generation is disabled.
1Channel event generation is enabled.

Bit 3 – EVIE Channel Event Input Enable

This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

Note: This bit is enable-protected.
ValueDescription
0Channel event action will not be executed on any incoming event.
1Channel event action will be executed on any incoming event.

Bits 2:0 – EVACT[2:0] Event Input Action

These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set.

This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

Note: This bit is enable-protected.
EVACT[2:0]NameDescription
0x0NOACTNo action
0x1TRIGNormal Transfer and Conditional Transfer on Strobe trigger
0x2CTRIGConditional transfer trigger
0x3CBLOCKConditional block transfer
0x4SUSPENDChannel suspend operation
0x5RESUMEChannel resume operation
0x6SSKIPSkip next block suspend action
0x7-Reserved