17.6.5.1.5 Digital Filter Selection

The PLL digital filter (PI controller) is automatically adjusted to provide a good compromise between stability and jitter. However, a software operation can override the filter setting using the Filter bit field in the DPLL Control B register (DPLLCTRLB.FILTER). The Low-Power Enable bit (DPLLCTRLB.LPEN) can be used to bypass the Time to Digital Converter (TDC) module.