3.3.14 UDDRC Refresh Timing Register


Bit	31	30	29	28	27	26	25	24
	T_RFC_NOM_X1_SEL				T_RFC_NOM_X1_X32[11:8]
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	23	22	21	20	19	18	17	16
	T_RFC_NOM_X1_X32[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	1	0	0	0	1	0


Bit	15	14	13	12	11	10	9	8
	LPDDR3_TREFBW_EN						T_RFC_MIN[9:8]
Access	R/W						R/W	R/W
Reset	0						0	0


Bit	7	6	5	4	3	2	1	0
	T_RFC_MIN[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	0	1	1	0	0

Bit 31 – T_RFC_NOM_X1_SEL

Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32.

This applies only when per-bank refresh is enabled (RFSHCTL0.per_bank_refresh=1); if per-bank refresh is not enabled, the x32 register values are used and this register field is ignored.

Programming mode: Dynamic - Refresh Related

Value	Description
0	x32 register values are used.
1	x1 register values are used.

Bits 27:16 – T_RFC_NOM_X1_X32[11:0]

Average time interval between refreshes per rank (Specification: 7.8 µs for DDR2 and DDR3. See JEDEC specification for LPDDR2 and LPDDR3).

When the controller is operating in 1:1 mode, set this register to RoundDown(tREFI/tCK).

When the controller is operating in 1:2 mode, set this register to RoundDown(RoundDown(tREFI/tCK)/2).

In both the above cases, if RFSHTMG.t_rfc_nom_x1_sel = 0, divide the above result by 32 and round down.

For LPDDR2/LPDDR3:

If using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), use tREFIab in the above calculations.
If using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), use tREFIpb in the above calculations.

Note that:

RFSHTMG.t_rfc_nom_x1_x32 must be greater than 0x1.
If RFSHTMG.t_rfc_nom_x1_sel == 1, RFSHTMG.t_rfc_nom_x1_x32 must be greater than RFSHTMG.t_rfc_min.
If RFSHTMG.t_rfc_nom_x1_sel == 0, RFSHTMG.t_rfc_nom_x1_x32 * 32 must be greater than RFSHTMG.t_rfc_min.
In Fixed 1x mode: RFSHTMG.t_rfc_nom_x1_x32 must be less than or equal to 0xFFE.

Unit: DFI clock cycles or multiples of 32 DFI clock cycles, depending on RFSHTMG.t_rfc_nom_x1_sel.

Programming mode: Dynamic - Refresh Related

Bit 15 – LPDDR3_TREFBW_EN

Used only when LPDDR3 memory type is connected. Should only be changed when UDDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not.

Programming mode: Static

Value	Description
0	tREFBW parameter not used.
1	tREFBW parameter used.

Bits 9:0 – T_RFC_MIN[9:0] tRFC (min): Minimum time from refresh to refresh or activate.

When the controller is operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK).

When the controller is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2).

In LPDDR2/LPDDR3 mode:

If using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab.
If using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb.

Unit: DFI clock cycles.

Programming mode: Dynamic - Refresh Related

Name:	UDDRC_RFSHTMG
Offset:	0x064
Reset:	0x0062008C
Property:	Read/Write