3.3.35 UDDRC ZQ Control Register 0
| Name: | UDDRC_ZQCTL0 |
| Offset: | 0x180 |
| Reset: | 0x02000040 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DIS_AUTO_ZQ | DIS_SRX_ZQCL | ZQ_RESISTOR_SHARED | T_ZQ_LONG_NOP[10:8] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| T_ZQ_LONG_NOP[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_ZQ_SHORT_NOP[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_ZQ_SHORT_NOP[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – DIS_AUTO_ZQ
This is only present for designs supporting DDR3 or LPDDR2/LPDDR3 devices.
Programming Mode: Dynamic
| Value | Description |
|---|---|
| 0 | Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. |
| 1 | Disable UDDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. |
Bit 30 – DIS_SRX_ZQCL
This is only present for designs supporting DDR3 or LPDDR2/LPDDR3 devices.
Programming Mode: Quasi-dynamic Group 2, Group 4
| Value | Description |
|---|---|
| 0 | Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3, LPDDR2 or LPDDR3 mode. |
| 1 | Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3, LPDDR2 or LPDDR3 mode. |
Bit 29 – ZQ_RESISTOR_SHARED
This is only present for designs supporting DDR3 or LPDDR2/LPDDR3 devices.
Programming Mode: Static
| Value | Description |
|---|---|
| 0 | ZQ resistor is not shared. |
| 1 | Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. |
Bits 26:16 – T_ZQ_LONG_NOP[10:0]
tZQoper for DDR3, tZQCL for LPDDR2/LPDDR3: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM.
When the controller is operating in 1:2 frequency ratio mode:
DDR3: program this to tZQoper/2 and round it up to the next integer value.
LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value.
This is only present for designs supporting DDR3 or LPDDR2/LPDDR3 devices.
Unit: DFI clock cycles.
Programming Mode: Static
Bits 9:0 – T_ZQ_SHORT_NOP[9:0]
tZQCS for DDR3/DD4/LPDDR2/LPDDR3: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value.
This is only present for designs supporting DDR3 or LPDDR2/LPDDR3 devices.
Unit: DFI clock cycles.
Programming Mode: Static