Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
- 3.1 Overview
- 3.2 Static Memory Controller (SMC)
- 3.3 Universal DDR Memory Controller (UDDRC)
  - 3.3.1 Description
  - 3.3.2 Embedded Characteristics
  - 3.3.3 Block Diagram
  - 3.3.4 I/O Lines Description
  - 3.3.5 Functional Description
  - 3.3 Register Summary
    - 3.3.1 UDDRC Host Register 0
      UDDRC Host Register 0
    - 3.3.2 UDDRC Operating Mode Status Register
      UDDRC Operating Mode Status Register
    - 3.3.3 UDDRC Mode Register Read/Write Control Register 0
      UDDRC Mode Register Read/Write Control Register 0
    - 3.3.4 UDDRC Mode Register Read/Write Control Register 1
      UDDRC Mode Register Read/Write Control Register 1
    - 3.3.5 UDDRC Mode Register Read/Write Status Register
      UDDRC Mode Register Read/Write Status Register
    - 3.3.6 UDDRC Temperature Derate Enable Register
      UDDRC Temperature Derate Enable Register
    - 3.3.7 UDDRC Temperature Derate Interval Register
      UDDRC Temperature Derate Interval Register
    - 3.3.8 UDDRC Temperature Derate Control Register
      UDDRC Temperature Derate Control Register
    - 3.3.9 UDDRC Low Power Control Register
      UDDRC Low Power Control Register
    - 3.3.10 UDDRC Low Power Timing Register
      UDDRC Low Power Timing Register
    - 3.3.11 UDDRC Hardware Low Power Control Register
      UDDRC Hardware Low Power Control Register
    - 3.3.12 UDDRC Refresh Control Register 0
      UDDRC Refresh Control Register 0
    - 3.3.13 UDDRC Refresh Control Register 3
      UDDRC Refresh Control Register 3
    - 3.3.14 UDDRC Refresh Timing Register
      UDDRC Refresh Timing Register
    - 3.3.15 UDDRC CRC Parity Control Register 0
      UDDRC CRC Parity Control Register 0
    - 3.3.16 UDDRC CRC Parity Status Register
      UDDRC CRC Parity Status Register
    - 3.3.17 UDDRC SDRAM Initialization Register 0
      UDDRC SDRAM Initialization Register 0
    - 3.3.18 UDDRC SDRAM Initialization Register 1
      UDDRC SDRAM Initialization Register 1
    - 3.3.19 UDDRC SDRAM Initialization Register 2
      UDDRC SDRAM Initialization Register 2
    - 3.3.20 UDDRC SDRAM Initialization Register 3
      UDDRC SDRAM Initialization Register 3
    - 3.3.21 UDDRC SDRAM Initialization Register 4
      UDDRC SDRAM Initialization Register 4
    - 3.3.22 UDDRC SDRAM Initialization Register 5
      UDDRC SDRAM Initialization Register 5
    - 3.3.23 UDDRC DIMM Control Register
      UDDRC DIMM Control Register
    - 3.3.24 UDDRC SDRAM Timing Register 0
      UDDRC SDRAM Timing Register 0
    - 3.3.25 UDDRC SDRAM Timing Register 1
      UDDRC SDRAM Timing Register 1
    - 3.3.26 UDDRC SDRAM Timing Register 2
      UDDRC SDRAM Timing Register 2
    - 3.3.27 UDDRC SDRAM Timing Register 3
      UDDRC SDRAM Timing Register 3
    - 3.3.28 UDDRC SDRAM Timing Register 4
      UDDRC SDRAM Timing Register 4
    - 3.3.29 UDDRC SDRAM Timing Register 5
      UDDRC SDRAM Timing Register 5
    - 3.3.30 UDDRC SDRAM Timing Register 6
      UDDRC SDRAM Timing Register 6
    - 3.3.31 UDDRC SDRAM Timing Register 7
      UDDRC SDRAM Timing Register 7
    - 3.3.32 UDDRC SDRAM Timing Register 8
      UDDRC SDRAM Timing Register 8
    - 3.3.33 UDDRC SDRAM Timing Register 14
      UDDRC SDRAM Timing Register 14
    - 3.3.34 UDDRC SDRAM Timing Register 15
      UDDRC SDRAM Timing Register 15
    - 3.3.35 UDDRC ZQ Control Register 0
      UDDRC ZQ Control Register 0
    - 3.3.36 UDDRC ZQ Control Register 1
      UDDRC ZQ Control Register 1
    - 3.3.37 UDDRC ZQ Control Register 2
      UDDRC ZQ Control Register 2
    - 3.3.38 UDDRC ZQ Status Register
      UDDRC ZQ Status Register
    - 3.3.39 UDDRC DFI Timing Register 0
      UDDRC DFI Timing Register 0
    - 3.3.40 UDDRC DFI Timing Register 1
      UDDRC DFI Timing Register 1
    - 3.3.41 UDDRC DFI Low Power Configuration Register 0
      UDDRC DFI Low Power Configuration Register 0
    - 3.3.42 UDDRC DFI Update Register 0
      UDDRC DFI Update Register 0
    - 3.3.43 UDDRC DFI Update Register 1
      UDDRC DFI Update Register 1
    - 3.3.44 UDDRC DFI Update Register 2
      UDDRC DFI Update Register 2
    - 3.3.45 UDDRC DFI Miscellaneous Control Register
      UDDRC DFI Miscellaneous Control Register
    - 3.3.46 UDDRC DFI Status Register
      UDDRC DFI Status Register
    - 3.3.47 UDDRC DFI PHY Host
      UDDRC DFI PHY Host
    - 3.3.48 UDDRC Address Map Register 1
      UDDRC Address Map Register 1
    - 3.3.49 UDDRC Address Map Register 2
      UDDRC Address Map Register 2
    - 3.3.50 UDDRC Address Map Register 3
      UDDRC Address Map Register 3
    - 3.3.51 UDDRC Address Map Register 4
      UDDRC Address Map Register 4
    - 3.3.52 UDDRC Address Map Register 5
      UDDRC Address Map Register 5
    - 3.3.53 UDDRC Address Map Register 6
      UDDRC Address Map Register 6
    - 3.3.54 UDDRC Address Map Register 9
      UDDRC Address Map Register 9
    - 3.3.55 UDDRC Address Map Register 10
      UDDRC Address Map Register 10
    - 3.3.56 UDDRC Address Map Register 11
      UDDRC Address Map Register 11
    - 3.3.57 UDDRC ODT Configuration Register
      UDDRC ODT Configuration Register
    - 3.3.58 UDDRC ODT/Rank Map Register
      UDDRC ODT/Rank Map Register
    - 3.3.59 UDDRC Scheduler Control Register 0
      UDDRC Scheduler Control Register 0
    - 3.3.60 UDDRC Scheduler Control Register 1
      UDDRC Scheduler Control Register 1
    - 3.3.61 UDDRC High Priority Read CAM Register 1
      UDDRC High Priority Read CAM Register 1
    - 3.3.62 UDDRC Low Priority Read CAM Register 1
      UDDRC Low Priority Read CAM Register 1
    - 3.3.63 UDDRC Write CAM Register 1
      UDDRC Write CAM Register 1
    - 3.3.64 UDDRC Debug Register 0
      UDDRC Debug Register 0
    - 3.3.65 UDDRC Debug Register 1
      UDDRC Debug Register 1
    - 3.3.66 UDDRC CAM Debug Register
      UDDRC CAM Debug Register
    - 3.3.67 UDDRC Command Debug Register
      UDDRC Command Debug Register
    - 3.3.68 UDDRC Status Debug Register
      UDDRC Status Debug Register
    - 3.3.69 UDDRC Software Register Programming Control Enable
      UDDRC Software Register Programming Control Enable
    - 3.3.70 UDDRC Software Register Programming Control Status
      UDDRC Software Register Programming Control Status
    - 3.3.71 UDDRC AXI Poison Configuration Register. Common for all AXI ports
      UDDRC AXI Poison Configuration Register. Common for all AXI ports
    - 3.3.72 UDDRC AXI Poison Status Register
      UDDRC AXI Poison Status Register
    - 3.3.73 UDDRC Temperature Derate Status Register
      UDDRC Temperature Derate Status Register
    - 3.3.74 UDDRC Port Status Register
      UDDRC Port Status Register
    - 3.3.75 UDDRC Port Common Configuration Register
      UDDRC Port Common Configuration Register
    - 3.3.76 UDDRC AXI Port 0 Configuration Read Register
      UDDRC AXI Port 0 Configuration Read Register
    - 3.3.77 UDDRC AXI Port 0 Configuration Write Register
      UDDRC AXI Port 0 Configuration Write Register
    - 3.3.78 UDDRC AXI Port 0 Control Register
      UDDRC AXI Port 0 Control Register
    - 3.3.79 UDDRC AXI Port 0 Read QoS Configuration Register 0
      UDDRC AXI Port 0 Read QoS Configuration Register 0
    - 3.3.80 UDDRC AXI Port 0 Read QoS Configuration Register 1
      UDDRC AXI Port 0 Read QoS Configuration Register 1
    - 3.3.81 UDDRC AXI Port 0 Write QoS Configuration Register 0
      UDDRC AXI Port 0 Write QoS Configuration Register 0
    - 3.3.82 UDDRC AXI Port 0 Write QoS Configuration Register 1
      UDDRC AXI Port 0 Write QoS Configuration Register 1
    - 3.3.83 UDDRC AXI Port 1 Configuration Read Register
      UDDRC AXI Port 1 Configuration Read Register
    - 3.3.84 UDDRC AXI Port 1 Configuration Write Register
      UDDRC AXI Port 1 Configuration Write Register
    - 3.3.85 UDDRC AXI Port 1 Control Register
      UDDRC AXI Port 1 Control Register
    - 3.3.86 UDDRC AXI Port 1 Read QoS Configuration Register 0
      UDDRC AXI Port 1 Read QoS Configuration Register 0
    - 3.3.87 UDDRC AXI Port 1 Read QoS Configuration Register 1
      UDDRC AXI Port 1 Read QoS Configuration Register 1
    - 3.3.88 UDDRC AXI Port 1 Write QoS Configuration Register 0
      UDDRC AXI Port 1 Write QoS Configuration Register 0
    - 3.3.89 UDDRC AXI Port 1 Write QoS Configuration Register 1
      UDDRC AXI Port 1 Write QoS Configuration Register 1
    - 3.3.90 UDDRC AXI Port 2 Configuration Read Register
      UDDRC AXI Port 2 Configuration Read Register
    - 3.3.91 UDDRC AXI Port 2 Configuration Write Register
      UDDRC AXI Port 2 Configuration Write Register
    - 3.3.92 UDDRC AXI Port 2 Control Register
      UDDRC AXI Port 2 Control Register
    - 3.3.93 UDDRC AXI Port 2 Read QoS Configuration Register 0
      UDDRC AXI Port 2 Read QoS Configuration Register 0
    - 3.3.94 UDDRC AXI Port 2 Read QoS Configuration Register 1
      UDDRC AXI Port 2 Read QoS Configuration Register 1
    - 3.3.95 UDDRC AXI Port 2 Write QoS Configuration Register 0
      UDDRC AXI Port 2 Write QoS Configuration Register 0
    - 3.3.96 UDDRC AXI Port 2 Write QoS Configuration Register 1
      UDDRC AXI Port 2 Write QoS Configuration Register 1
    - 3.3.97 UDDRC AXI Port 3 Configuration Read Register
      UDDRC AXI Port 3 Configuration Read Register
    - 3.3.98 UDDRC AXI Port 3 Configuration Write Register
      UDDRC AXI Port 3 Configuration Write Register
    - 3.3.99 UDDRC AXI Port 3 Control Register
      UDDRC AXI Port 3 Control Register
    - 3.3.100 UDDRC AXI Port 3 Read QoS Configuration Register 0
      UDDRC AXI Port 3 Read QoS Configuration Register 0
    - 3.3.101 UDDRC AXI Port 3 Read QoS Configuration Register 1
      UDDRC AXI Port 3 Read QoS Configuration Register 1
    - 3.3.102 UDDRC AXI Port 3 Write QoS Configuration Register 0
      UDDRC AXI Port 3 Write QoS Configuration Register 0
    - 3.3.103 UDDRC AXI Port 3 Write QoS Configuration Register 1
      UDDRC AXI Port 3 Write QoS Configuration Register 1
    - 3.3.104 UDDRC AXI Port 4 Configuration Read Register
      UDDRC AXI Port 4 Configuration Read Register
    - 3.3.105 UDDRC AXI Port 4 Configuration Write Register
      UDDRC AXI Port 4 Configuration Write Register
    - 3.3.106 UDDRC AXI Port 4 Control Register
      UDDRC AXI Port 4 Control Register
    - 3.3.107 UDDRC AXI Port 4 Read QoS Configuration Register 0
      UDDRC AXI Port 4 Read QoS Configuration Register 0
    - 3.3.108 UDDRC AXI Port 4 Read QoS Configuration Register 1
      UDDRC AXI Port 4 Read QoS Configuration Register 1
    - 3.3.109 UDDRC AXI Port 4 Write QoS Configuration Register 0
      UDDRC AXI Port 4 Write QoS Configuration Register 0
    - 3.3.110 UDDRC AXI Port 4 Write QoS Configuration Register 1
      UDDRC AXI Port 4 Write QoS Configuration Register 1
    - 3.3.111 UDDRC SAR Base Address Register 0
      UDDRC SAR Base Address Register 0
    - 3.3.112 UDDRC SAR Size Register 0
      UDDRC SAR Size Register 0
    - 3.3.113 UDDRC FREQ1 Temperature Derate Enable Register
      UDDRC FREQ1 Temperature Derate Enable Register
    - 3.3.114 UDDRC FREQ1 Temperature Derate Interval Register
      UDDRC FREQ1 Temperature Derate Interval Register
    - 3.3.115 UDDRC FREQ1 Low Power Timing Register
      UDDRC FREQ1 Low Power Timing Register
    - 3.3.116 UDDRC FREQ1 Refresh Control Register 0
      UDDRC FREQ1 Refresh Control Register 0
    - 3.3.117 UDDRC FREQ1 Refresh Timing Register
      UDDRC FREQ1 Refresh Timing Register
    - 3.3.118 UDDRC FREQ1 SDRAM Initialization Register 3
      UDDRC FREQ1 SDRAM Initialization Register 3
    - 3.3.119 UDDRC FREQ1 SDRAM Initialization Register 4
      UDDRC FREQ1 SDRAM Initialization Register 4
    - 3.3.120 UDDRC FREQ1 SDRAM Timing Register 0
      UDDRC FREQ1 SDRAM Timing Register 0
    - 3.3.121 UDDRC FREQ1 SDRAM Timing Register 1
      UDDRC FREQ1 SDRAM Timing Register 1
    - 3.3.122 UDDRC FREQ1 SDRAM Timing Register 2
      UDDRC FREQ1 SDRAM Timing Register 2
    - 3.3.123 UDDRC FREQ1 SDRAM Timing Register 3
      UDDRC FREQ1 SDRAM Timing Register 3
    - 3.3.124 UDDRC FREQ1 SDRAM Timing Register 4
      UDDRC FREQ1 SDRAM Timing Register 4
    - 3.3.125 UDDRC FREQ1 SDRAM Timing Register 5
      UDDRC FREQ1 SDRAM Timing Register 5
    - 3.3.126 UDDRC FREQ1 SDRAM Timing Register 6
      UDDRC FREQ1 SDRAM Timing Register 6
    - 3.3.127 UDDRC FREQ1 SDRAM Timing Register 7
      UDDRC FREQ1 SDRAM Timing Register 7
    - 3.3.128 UDDRC FREQ1 SDRAM Timing Register 8
      UDDRC FREQ1 SDRAM Timing Register 8
    - 3.3.129 UDDRC FREQ1 SDRAM Timing Register 14
      UDDRC FREQ1 SDRAM Timing Register 14
    - 3.3.130 UDDRC FREQ1 SDRAM Timing Register 15
      UDDRC FREQ1 SDRAM Timing Register 15
    - 3.3.131 UDDRC FREQ1 ZQ Control Register 0
      UDDRC FREQ1 ZQ Control Register 0
    - 3.3.132 UDDRC FREQ1 DFI Timing Register 0
      UDDRC FREQ1 DFI Timing Register 0
    - 3.3.133 UDDRC FREQ1 DFI Timing Register 1
      UDDRC FREQ1 DFI Timing Register 1
    - 3.3.134 UDDRC FREQ1 ODT Configuration Register
      UDDRC FREQ1 ODT Configuration Register
- 3.4 DDR/LPDDR Physical Interface (DDR3PHY)
4 System Controller
5 Analog Subsystem
6 Image Subsystem
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Glossary
13 Revision History
Microchip Information

3.3.75 UDDRC Port Common Configuration Register

Name:	UDDRC_PCCFG
Offset:	0x400
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
								BL_EXP_MODE
Access								R/W
Reset								0


Bit	7	6	5	4	3	2	1	0
				PAGEMATCH_LIMIT				GO2CRITICAL_EN
Access				R/W				R/W
Reset				0				0

Bit 8 – BL_EXP_MODE

Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit.

This applies to both reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect.

Functionality is also not supported if Data Channel Interleave is enabled

Programming Mode: Static

Bit 4 – PAGEMATCH_LIMIT

Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions.

Programming Mode: Static

Bit 0 – GO2CRITICAL_EN

If set to 1 (enabled), sets the co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from the AXI host. If set to 0 (disabled), the co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.

For uPCTL2, this register field must be set to 0

Programming Mode: Static

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