6.5.4.1 GPU2DC Clock Control Register
| Name: | GPU2DC_AQHiClockControl |
| Offset: | 0x00 |
| Reset: | 0x00070900 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ISOLATE_GPU | IDLE_VG | IDLE2_D | IDLE3_D | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SOFT_RESET | DISABLE_RAM_CLOCK_GATING | FSCALE_CMD_LOAD | FSCALE_VAL[6] | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FSCALE_VAL[5:0] | CLK2D_DIS | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 19 – ISOLATE_GPU Isolate GPU
When set, disables the AXI interface. Software must ensure that all engines are idle before enabling this bit.
| Value | Name | Description |
|---|---|---|
| 0 | FALSE | GPU2DC isolation is not active. |
| 1 | TRUE | AXI interface is disabled and GPU2DC isolated. |
Bit 18 – IDLE_VG VG Pipe Idle
| Value | Name | Description |
|---|---|---|
| 0 | FALSE | VG pipe is not idle. |
| 1 | TRUE | VG pipe is idle. |
Bit 17 – IDLE2_D 2D Pipe Idle
| Value | Name | Description |
|---|---|---|
| 0 | ACTIVE | 2D pipe is active. |
| 1 | IDLE | 2D pipe is idle. |
Bit 16 – IDLE3_D 3D Pipe Idle
| Value | Name | Description |
|---|---|---|
| 0 | NOT_APPLICABLE | Not applicable, always read as ‘1’. |
| 1 | NOT_PRESENT | IDLE 3D pipe is not present. |
Bit 12 – SOFT_RESET GPU2DC Software Reset
| Value | Description |
|---|---|
| 0 | Releases the soft reset. |
| 1 | Soft resets the module. |
Bit 10 – DISABLE_RAM_CLOCK_GATING Disable RAM Clock Gating
| Value | Description |
|---|---|
| 0 | Functional clock gating is enabled for GPU2DC memories. |
| 1 | Functional clock gating is disabled for GPU2DC memories. |
Bit 9 – FSCALE_CMD_LOAD Core Clock Scaling Enable
| Value | Description |
|---|---|
| 0 | Clock scaling disabled. |
| 1 | Clock scaling enabled. |
Bits 8:2 – FSCALE_VAL[6:0] Core Clock Frequency Scale Factor
Bit 1 – CLK2D_DIS Software Core Clock Disable
| Value | Description |
|---|---|
| 0 | Clock is enabled. |
| 1 | Clock is disabled. |