6.5.4.4 GPU2DC AXI Status Register
| Name: | GPU2DC_AQAxiStatus |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DET_RD_ERR | DET_WR_ERR | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RD_ERR_ID[3:0] | WR_ERR_ID[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 9 – DET_RD_ERR Detect Read Error
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | Error detected on read. |
Bit 8 – DET_WR_ERR Detect Write Error
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | Error detected on write. |
Bits 7:4 – RD_ERR_ID[3:0] ReadID Caused Illegal Accesses
Valid only when DET_RD_ERR is set.
Bits 3:0 – WR_ERR_ID[3:0] WriteID Caused Illegal Accesses
Valid only when DET_WR_ERR is set.