6.5.4.6 GPU2DC Interrupt Enable Register
| Name: | GPU2DC_AQIntrEnbl |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| AXI_EXCEPTION_INTR_ENBL | MMU_EXCEPTION_INTR_ENBL | INTR_ENBL_VEC[28:24] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| INTR_ENBL_VEC[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INTR_ENBL_VEC[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INTR_ENBL_VEC[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – AXI_EXCEPTION_INTR_ENBL Interrupt Enable for an AXI Exception
Bit 30 – MMU_EXCEPTION_INTR_ENBL Interrupt Enable for an MMU Exception
Bits 28:0 – INTR_ENBL_VEC[28:0] Interrupt Enable
| Value | Description |
|---|---|
| 0 | Disables the interrupt for the corresponding event. |
| 1 | Enables the interrupt for the corresponding event. |