6.5.4.5 GPU2DC Interrupt Acknowledge Register

Name:	GPU2DC_AQIntrAcknowledge
Offset:	0x10
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
	AXI_EXCEPTION	MMU_EXCEPTION		INTR_VEC[28:24]
Access	R	R		R	R	R	R	R
Reset	0	0		0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	INTR_VEC[23:16]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	INTR_VEC[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	INTR_VEC[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 31 – AXI_EXCEPTION AXI Exception

Value	Description
0	No AXI exception.
1	AXI exception.

Bit 30 – MMU_EXCEPTION MMU Exception

Value	Description
0	No MMU exception.
1	MMU exception.

Bits 28:0 – INTR_VEC[28:0] Event ID from ID28 to ID0

Value	Description
0	Event IDx is not active.
1	Event IDx is active

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